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PDF MB85RS1MT Data sheet ( Hoja de datos )
| Número de pieza | MB85RS1MT | |
| Descripción | 1M (128K x 8) Bit SPI | |
| Fabricantes | Fujitsu | |
| Logotipo |  |
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FUJITSU SEMICONDUCTOR
DATA SHEET
Memory FRAM
DS501-00022-6v0-E
1M (128 K × 8) Bit SPI
MB85RS1MT
■ DESCRIPTION
MB85RS1MT is a FRAM (Ferroelectric Random Access Memory) chip in a configuration of 131,072
words × 8 bits, using the ferroelectric process and silicon gate CMOS process technologies for forming the
nonvolatile memory cells.
MB85RS1MT adopts the Serial Peripheral Interface (SPI).
The MB85RS1MT is able to retain data without using a back-up battery, as is needed for SRAM.
The memory cells used in the MB85RS1MT can be used for 1013 read/write operations, which is a significant
improvement over the number of read and write operations supported by Flash memory and E2PROM.
MB85RS1MT does not take long time to write data like Flash memories or E2PROM, and MB85RS1MT takes
no wait time.
■ FEATURES
• Bit configuration
: 131,072 words × 8 bits
• Serial Peripheral Interface
: SPI (Serial Peripheral Interface)
Correspondent to SPI mode 0 (0, 0) and mode 3 (1, 1)
• Operating frequency
: 1.8 V to 2.7 V, 25 MHz (Max)
2.7 V to 3.6 V, 30 MHz (Max)
For FSTRD command 2.7 V to 3.6 V, 40 MHz (Max)
• High endurance
: 1013 times / byte
• Data retention
: 10 years (+85 °C), 95 years ( + 55 °C), over 200 years ( + 35 °C)
• Operating power supply voltage : 1.8 V to 3.6 V
• Low power consumption
: Operating power supply current 9.5 mA (Max@30 MHz)
Standby current 120 μA (Max)
Sleep current 10 μA (Max)
• Operation ambient temperature range : -40 °C to +85 °C
• Package
: 8-pin plastic SOP (FPT-8P-M02)
8-pin plastic WLP (WLP-8P-M01)
8-pin plastic DIP (DIP-8P-M03)
RoHS compliant
Copyright 2013-2016 FUJITSU SEMICONDUCTOR LIMITED
2016.10
1 page  
MB85RS1MT
■ SPI MODE
MB85RS1MT corresponds to the SPI mode 0 (CPOL = 0, CPHA = 0) , and SPI mode 3 (CPOL = 1, CPHA = 1) .
CS
SCK
SI 7 6 5 4 3 2 1 0
MSB
SPI Mode 0
LSB
CS
SCK
SI
76543210
MSB
SPI Mode 3
LSB
DS501-00022-6v0-E
5
5 Page 
MB85RS1MT
• FSTRD
The FSTRD command reads FRAM memory cell array data. Arbitrary 24 bits address and op-code of FSTRD
are input to SI followed by 8 bits dummy. The 7-bit upper address bit is invalid. Then, 8-cycle clock is input
to SCK. SO is output synchronously to the falling edge of SCK. While reading, the SI value is invalid. When
CS is risen, the FSTRD command is completed, but keeps on reading with automatic address increment
which is enabled by continuously sending clocks to SCK in unit of 8 cycles before CS rising. When it reaches
the most significant address, it rolls over to the starting address, and reading cycle keeps on infinitely. FSTRD
command is applicable to “Up to 25 MHz (1.8 V to 2.7 V) and 40 MHz (2.7 V to 3.6 V) operation”.
CS
SCK
SI
SO
0 1 2 3 4 5 6 7 8 9 10 11 12 13 1415 29 30 31 32 33 38 39 40 41 42 43 44 45 46 47
OP-CODE
24-bit Address
0 0 0 0 1 0 1 1 X X X X X X X 16
MSB
High-Z
8-bit Dummy
2 1 0 XX
X X Invalid
LSB MSB Data Out LSB
76543210
Invalid
• RDID
The RDID command reads fixed Device ID. After performing RDID op-code to SI, 32-cycle clock is input to
SCK. The SI value is invalid for this time. SO is output synchronously to a falling edge of SCK. The output
is in order of Manufacturer ID (8bit)/Continuation code (8bit)/Product ID (1st Byte)/Product ID (2nd Byte).
In the RDID command, SO holds the output state of the last bit in 32-bit Device ID until CS is risen. RDID
command is applicable to “Up to 25 MHz (1.8 V to 2.7 V) and 30 MHz (2.7 V to 3.6 V) operation”.
CS
SCK
0 1 2 3 4 5 6 7 8 9 10 11
31 32 33 34 35 36 37 38 39
SI
10011111
Invalid
High-Z
SO
Data Out
31 30 29 28
MSB
Data Out
876543210
LSB
Manufacturer ID
Continuation code
bit
7654321
0000010
0111111
Proprietary use
Product ID (1st Byte) 0 0 1 0
Density
011
Proprietary use
Product ID (2nd Byte) 0 0 0 0 0 0 1
0 Hex
0 04H Fujitsu
1 7FH
Hex
1 27H Density: 00111B = 1 Mbit
Hex
1 03H
DS501-00022-6v0-E
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MB85RS1MT.PDF ] | |
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