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CY14B101LA Schematic ( PDF Datasheet ) - Cypress Semiconductor

Teilenummer CY14B101LA
Beschreibung 1-Mbit (128 K x 8/64 K x 16) nvSRAM
Hersteller Cypress Semiconductor
Logo Cypress Semiconductor Logo 




Gesamt 30 Seiten
CY14B101LA Datasheet, Funktion
CY14B101LA
CY14B101NA
1-Mbit (128 K × 8/64 K × 16) nvSRAM
1-Mbit (128 K × 8/64 K × 16) nvSRAM
Features
20 ns, 25 ns, and 45 ns access times
Internally organized as 128 K × 8 (CY14B101LA) or 64 K × 16
(CY14B101NA)
Hands off automatic STORE on power-down with only a small
capacitor
STORE to QuantumTrap nonvolatile elements initiated by
software, device pin, or AutoStore on power-down
RECALL to SRAM initiated by software or power-up
Infinite read, write, and RECALL cycles
1 million STORE cycles to QuantumTrap
20 year data retention
Single 3 V +20% to –10% operation
Industrial temperature
Logic Block Diagram [1, 2, 3]
Packages
32-pin small-outline integrated circuit (SOIC)
44-/54-pin thin small outline package (TSOP) Type II
48-pin shrink small-outline package (SSOP)
48-ball fine-pitch ball grid array (FBGA)
Pb-free and restriction of hazardous substances (RoHS)
compliant
Functional Description
The Cypress CY14B101LA/CY14B101NA is a fast static RAM
(SRAM), with a nonvolatile element in each memory cell. The
memory is organized as 128 K bytes of 8 bits each or 64 K words
of 16 bits each. The embedded nonvolatile elements incorporate
QuantumTrap technology, producing the world’s most reliable
nonvolatile memory. The SRAM provides infinite read and write
cycles, while independent nonvolatile data resides in the highly
reliable QuantumTrap cell. Data transfers from the SRAM to the
nonvolatile elements (the STORE operation) takes place
automatically at power-down. On power-up, data is restored to
the SRAM (the RECALL operation) from the nonvolatile memory.
Both the STORE and RECALL operations are also available
under software control.
For a complete list of related resources, click here.
Quatrum Trap
VCC
VCAP
1024 X 1024
A5
R
O
A6 W
STORE
POWER
CONTROL
A7
A8
A9
A12
RECALL
D
E
C STATIC RAM
STORE/RECALL
CONTROL
HSB
A13 O ARRAY
A14
A15
A16
D 1024 X 1024
E
R
SOFTWARE
DETECT
A14 - A2
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I
N
P
U
T
B COLUMN I/O
U
F
F
E
R COLUMN DEC
S
A0 A1 A2 A3 A4 A10 A11
OE
WE
CE
BLE
BHE
Notes
1. Address A0–A16 for × 8 configuration and Address A0–A15 for × 16 configuration.
2. Data DQ0–DQ7 for × 8 configuration and Data DQ0–DQ15 for × 16 configuration.
3. BHE and BLE are applicable for × 16 configuration only.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-42879 Rev. *Q
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 12, 2014






CY14B101LA Datasheet, Funktion
CY14B101LA
CY14B101NA
Device Operation
The CY14B101LA/CY14B101NA nvSRAM is made up of two
functional components paired in the same physical cell. They are
an SRAM memory cell and a nonvolatile QuantumTrap cell. The
SRAM memory cell operates as a standard fast static RAM. Data
in the SRAM is transferred to the nonvolatile cell (the STORE
operation), or from the nonvolatile cell to the SRAM (the RECALL
operation). Using this unique architecture, all cells are stored and
recalled in parallel. During the STORE and RECALL operations,
SRAM read and write operations are inhibited. The
CY14B101LA/CY14B101NA supports infinite reads and writes
similar to a typical SRAM. In addition, it provides infinite RECALL
operations from the nonvolatile cells and up to 1 million STORE
operations. See the Truth Table For SRAM Operations on page
18 for a complete description of read and write modes.
SRAM Read
The CY14B101LA/CY14B101NA performs a read cycle when
CE and OE are LOW and WE and HSB are HIGH. The address
specified on pins A0–16 or A0–15 determines which of the 131,072
data bytes or 65,536 words of 16 bits each are accessed. Byte
enables (BHE, BLE) determine which bytes are enabled to the
output, in the case of 16-bit words. When the read is initiated by
an address transition, the outputs are valid after a delay of tAA
(read cycle 1). If the read is initiated by CE or OE, the outputs
are valid at tACE or at tDOE, whichever is later (read cycle 2). The
data output repeatedly responds to address changes within the
tAA access time without the need for transitions on any control
input pins. This remains valid until another address change or
until CE or OE is brought HIGH, or WE or HSB is brought LOW.
SRAM Write
A write cycle is performed when CE and WE are LOW and HSB
is HIGH. The address inputs must be stable before entering the
write cycle and must remain stable until CE or WE goes HIGH at
the end of the cycle. The data on the common I/O pins DQ0–15
are written into the memory if the data is valid tSD before the end
of a WE-controlled write or before the end of a CE-controlled
write. The Byte Enable inputs (BHE, BLE) determine which bytes
are written, in the case of 16-bit words. Keep OE HIGH during
the entire write cycle to avoid data bus contention on common
I/O lines. If OE is left LOW, internal circuitry turns off the output
buffers tHZWE after WE goes LOW.
AutoStore Operation
The CY14B101LA/CY14B101NA stores data to the nvSRAM
using one of the following three storage operations: Hardware
STORE activated by HSB; Software STORE activated by an
address sequence; AutoStore on device power-down. The
AutoStore operation is a unique feature of QuantumTrap
technology and is enabled by default on the
CY14B101LA/CY14B101NA.
During a normal operation, the device draws current from VCC to
charge a capacitor connected to the VCAP pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the VCC pin drops below VSWITCH, the part
automatically disconnects the VCAP pin from VCC. A STORE
operation is initiated with power provided by the VCAP capacitor.
Note
14. HSB pin is not available in 44-pin TSOP II (× 16) package.
Note If the capacitor is not connected to VCAP pin, AutoStore
must be disabled using the soft sequence specified in Preventing
AutoStore on page 8. In case AutoStore is enabled without a
capacitor on VCAP pin, the device attempts an AutoStore
operation without sufficient charge to complete the store. This
corrupts the data stored in nvSRAM.
Figure 4 shows the proper connection of the storage capacitor
(VCAP) for automatic STORE operation. See the DC Electrical
Characteristics on page 9 for the size of VCAP. The voltage on
the VCAP pin is driven to VCC by a regulator on the chip. A pull-up
should be placed on WE to hold it inactive during power-up. This
pull-up is effective only if the WE signal is tristate during
power-up. Many MPUs tristate their controls on power-up. This
should be verified when using the pull-up. When the nvSRAM
comes out of power-on-RECALL, the MPU must be active or the
WE held inactive until the MPU comes out of reset.
To reduce unnecessary nonvolatile stores, AutoStore and
Hardware STORE operations are ignored unless at least one
write operation has taken place since the most recent STORE or
RECALL cycle. Software initiated STORE cycles are performed
regardless of whether a write operation has taken place. The
HSB signal is monitored by the system to detect if an AutoStore
cycle is in progress.
Figure 4. AutoStore Mode
VCC
0.1 uF
VCC
WE VCAP
VSS
VCAP
Hardware STORE Operation
The CY14B101LA/CY14B101NA provides the HSB[14] pin to
control and acknowledge the STORE operations. Use the HSB
pin to request a Hardware STORE cycle. When the HSB pin is
driven LOW, the CY14B101LA/CY14B101NA conditionally
initiates a STORE operation after tDELAY. An actual STORE cycle
only begins if a write to the SRAM has taken place since the last
STORE or RECALL cycle. The HSB pin also acts as an open
drain driver (internal 100 kweak pull-up resistor) that is
internally driven LOW to indicate a busy condition when the
STORE (initiated by any means) is in progress.
Note After each Hardware and Software STORE operation HSB
is driven HIGH for a short time (tHHHD) with standard output high
current and then remains HIGH by internal 100 kpull-up
resistor.
Document Number: 001-42879 Rev. *Q
Page 6 of 30

6 Page









CY14B101LA pdf, datenblatt
CY14B101LA
CY14B101NA
AC Switching Characteristics
Over the Operating Range
Parameters [24]
Cypress
Parameter
Alt Parameter
Description
SRAM Read Cycle
tACE
tACS
tRC[25]
tRC
tAA[26]
tAA
tDOE
tOE
tOHA[26]
tOH
tLZCE[27, 28]
tLZ
tHZCE[27, 28]
tHZ
tLZOE[27, 28]
tOLZ
tHZOE[27, 28]
tOHZ
tPU[27]
tPA
tPD[27]
tDBE[[27]
tLZBE[27]
tHZBE[27]
tPS
SRAM Write Cycle
Chip enable access time
Read cycle time
Address access time
Output enable to data valid
Output hold after address change
Chip enable to output active
Chip disable to output inactive
Output enable to output active
Output disable to output inactive
Chip enable to power active
Chip disable to power standby
Byte enable to data valid
Byte enable to output active
Byte disable to output inactive
tWC tWC
tPWE
tWP
tSCE
tCW
tSD tDW
tHD tDH
tAW tAW
tSA tAS
tHA tWR
tHZWE[27, 28, 29] tWZ
tLZWE[27, 28]
tOW
tBW
Write cycle time
Write pulse width
Chip enable to end of write
Data setup to end of write
Data hold after end of write
Address setup to end of write
Address setup to start of write
Address hold after end of write
Write enable to output disable
Output active after end of write
Byte enable to end of write
20 ns
25 ns
Min Max Min Max
– 20 – 25
20 – 25 –
– 20 – 25
– 10 – 12
3–3–
3–3–
– 8 – 10
0–0–
– 8 – 10
0–0–
– 20 – 25
– 10 – 12
0–0–
– 8 – 10
20 – 25 –
15 – 20 –
15 – 20 –
8 – 10 –
0–0–
15 – 20 –
0–0–
0–0–
– 8 – 10
3–3–
15 – 20 –
Switching Waveforms
Figure 6. SRAM Read Cycle #1 (Address Controlled) [25, 26, 30]
tRC
Address
Address Valid
45 ns
Min Max Unit
– 45 ns
45 ns
– 45 ns
– 20 ns
3 – ns
3 – ns
– 15 ns
0 – ns
– 15 ns
0 – ns
– 45 ns
– 20 ns
0 ns
– 15 ns
45 – ns
30 – ns
30 – ns
15 – ns
0 – ns
30 – ns
0 – ns
0 – ns
– 15 ns
3 – ns
30 – ns
tAA
Data Output
Previous Data Valid
tOHA
Output Data Valid
Notes
24. Test conditions assume signal transition time of 3 ns or less, timing reference levels of VCC/2, input pulse levels of 0 to VCC(typ), and output loading of the specified
IOL/IOH and load capacitance shown in Figure 5 on page 11.
25. WE must be HIGH during SRAM read cycles.
26. Device is continuously selected with CE, OE, and BHE/BLE LOW.
27. These parameters are guaranteed by design and are not tested.
28. Measured ±200 mV from steady state output voltage.
29. If WE is low when CE goes low, the outputs remain in the high impedance state.
30. HSB must remain HIGH during Read and Write cycles.
Document Number: 001-42879 Rev. *Q
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