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CY14E256LA Schematic ( PDF Datasheet ) - Cypress Semiconductor

Teilenummer CY14E256LA
Beschreibung 256-Kbit (32 K x 8) nvSRAM
Hersteller Cypress Semiconductor
Logo Cypress Semiconductor Logo 




Gesamt 19 Seiten
CY14E256LA Datasheet, Funktion
CY14E256LA
256-Kbit (32 K × 8) nvSRAM
256-Kbit (32 K × 8) nvSRAM
Features
25 ns and 45 ns access times
Internally organized as 32 K × 8 (CY14E256LA)
Hands-off automatic STORE on power-down with only a small
capacitor
STORE to QuantumTrap nonvolatile elements initiated by
software, device pin, or autostore on power-down
RECALL to SRAM initiated by software or power-up
Infinite read, write, and RECALL cycles
1 million STORE cycles to QuantumTrap
20-year data retention
Single 5 V + 10% operation
Industrial temperature
44-pin thin small-outline package (TSOP) Type II and 32-pin
small-outline integrated circuit (SOIC) package
Pb-free and restriction of hazardous substances (RoHS)
compliant
Functional Description
The Cypress CY14E256LA is a fast static RAM, with a
nonvolatile element in each memory cell. The memory is
organized as 32 KB. The embedded nonvolatile elements
incorporate QuantumTrap technology, producing the world’s
most reliable nonvolatile memory. The SRAM provides infinite
read and write cycles, while independent nonvolatile data
resides in the highly reliable QuantumTrap cell. Data transfers
from the SRAM to the nonvolatile elements (the STORE
operation) takes place automatically at power-down. On
power-up, data is restored to the SRAM (the RECALL operation)
from the nonvolatile memory. Both the STORE and RECALL
operations are also available under software control.
For a complete list of related documentation, click here.
Logic Block Diagram
A5
A6
A7
A8
A9
A 11
A 12
A 13
A 14
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
QuantumTrap
512 X 512
STORE
STATIC RAM
ARRAY
512 X 512
RECALL
COLUMN I/O
COLUMN DEC
A0 A1 A2 A3 A4 A10
VCC
VCAP
POWER
CONTROL
STORE/
RECALL
CONTROL
HSB
SOFTWARE
DETECT
-A13 A0
OE
CE
WE
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-54952 Rev. *K
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 14, 2014






CY14E256LA Datasheet, Funktion
CY14E256LA
Table 1. Mode Selection (continued)
CE
WE
OE
A14–A0[6]
Mode
I/O Power
L
H
L
0x0E38
Read SRAM
Output data
Active[8]
0x31C7
Read SRAM
Output data
0x03E0
Read SRAM
Output data
0x3C1F
Read SRAM
Output data
0x303F
Read SRAM
Output data
0x0B46
AutoStore enable Output data
L
H
L
0x0E38
Read SRAM
Output data
Active ICC2[8]
0x31C7
Read SRAM
Output data
0x03E0
Read SRAM
Output data
0x3C1F
Read SRAM
Output data
0x303F
Read SRAM
Output data
0x0FC0
Nonvolatile
Output high Z
STORE
L
H
L
0x0E38
Read SRAM
Output data
Active[8]
0x31C7
Read SRAM
Output data
0x03E0
Read SRAM
Output data
0x3C1F
Read SRAM
Output data
0x303F
Read SRAM
Output data
0x0C63
Nonvolatile
Output high Z
RECALL
Preventing AutoStore
The AutoStore function is disabled by initiating an AutoStore
disable sequence. A sequence of read operations is performed
in a manner similar to the Software STORE initiation. To initiate
the AutoStore disable sequence, the following sequence of CE
or OE controlled read operations must be performed:
1. Read address 0x0E38 Valid READ
2. Read address 0x31C7 Valid READ
3. Read address 0x03E0 Valid READ
4. Read address 0x3C1F Valid READ
5. Read address 0x303F Valid READ
6. Read address 0x0B45 AutoStore Disable
The AutoStore is reenabled by initiating an AutoStore enable
sequence. A sequence of read operations is performed in a
manner similar to the Software RECALL initiation. To initiate the
AutoStore enable sequence, the following sequence of CE or OE
controlled read operations must be performed:
1. Read address 0x0E38 Valid READ
2. Read address 0x31C7 Valid READ
3. Read address 0x03E0 Valid READ
4. Read address 0x3C1F Valid READ
5. Read address 0x303F Valid READ
6. Read address 0x0B46 AutoStore Enable
If the AutoStore function is disabled or reenabled, a manual
STORE operation (Hardware or Software) must be issued to
save the AutoStore state through subsequent power-down
cycles. The part comes from the factory with AutoStore enabled
and 0x00 written in all cells.
Data Protection
The CY14E256LA protects data from corruption during low
voltage conditions by inhibiting all externally initiated STORE
and write operations. The low voltage condition is detected when
VCC is less than VSWITCH. If the CY14E256LA is in a write mode
(both CE and WE are LOW) at power-up, after a RECALL or
STORE, the write is inhibited until the SRAM is enabled after
tLZHSB (HSB to output active). This protects against inadvertent
writes during power-up or brown out conditions.
Note
8. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle.
Document Number: 001-54952 Rev. *K
Page 6 of 19

6 Page









CY14E256LA pdf, datenblatt
CY14E256LA
AutoStore/Power-up RECALL
Over the Operating Range
Parameter
Description
tHRECALL[25]
tSTORE[26]
tDELAY[27]
VSWITCH
tVCCRISE[28]
VHDIS[28]
tLZHSB[28]
tHHHD[28]
Power-up RECALL duration
STORE cycle duration
Time allowed to complete SRAM write cycle
Low voltage trigger level
VCC rise time
HSB output disable voltage
HSB to output active time
HSB high active time
CY14E256LA
Min Max
– 20
–8
– 25
– 4.4
150 –
– 1.9
–5
– 500
Unit
ms
ms
ns
V
µs
V
µs
ns
Switching Waveforms
Figure 8. AutoStore or Power-up RECALL [29]
VCC
VSWITCH
VHDIS
HSB OUT
AutoStore
POWER-
UP
RECALL
Read & Write
Inhibited
(RWI)
tVCCRISE
Note30
tHHHD
Note26
tSTORE
tLZHSB
tHRECALL
tDELAY
tHHHD
Note26 tSTORE
Note30
tDELAY
tLZHSB
tHRECALL
POWER-UP
RECALL
Read & Write
BROWN POWER-UP
OUT
RECALL
AutoStore
Read & Write
POWER
DOWN
AutoStore
Notes
25. tHRECALL starts from the time VCC rises above VSWITCH.
26. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place.
27. On a Hardware STORE and AutoStore initiation, SRAM write operation continues to be enabled for time tDELAY.
28. These parameters are guaranteed by design and are not tested.
29. Read and Write cycles are ignored during STORE, RECALL, and while VCC is less than VSWITCH.
30. During power-up and power-down, HSB glitches when HSB pin is pulled up through an external resistor.
Document Number: 001-54952 Rev. *K
Page 12 of 19

12 Page





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