PDF STK11C68 Data sheet ( Hoja de datos )

Número de pieza	STK11C68
Descripción	64-Kbit (8 K x 8) SoftStore nvSRAM
Fabricantes	Cypress Semiconductor
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No Preview Available ! STK11C68 64-Kbit (8 K × 8) SoftStore nvSRAM Features ■ 25 ns, 35 ns, and 45 ns access times ■ Pin compatible with industry standard SRAMs ■ Software initiated nonvolatile STORE ■ Unlimited Read and Write endurance ■ Automatic RECALL to SRAM on power up ■ Unlimited RECALL cycles ■ 1,000,000 STORE cycles ■ 100 year data retention ■ Single 5 V+10% operation ■ Commercial and industrial temperature ■ 28-pin (330 mil) SOIC package ■ 28-pin (300 mil) CDIP and 28-pad (350 mil) LCC packages ■ RoHS compliance Functional Description The Cypress STK11C68 is a 64Kb fast static RAM with a nonvol- atile element in each memory cell. The embedded nonvolatile elements incorporate QuantumTrap technology producing the world’s most reliable nonvolatile memory. The SRAM provides unlimited read and write cycles, while independent nonvolatile data resides in the highly reliable QuantumTrap cell. Data transfers under software control from SRAM to the nonvolatile elements (the STORE operation). On power up, data is automat- ically restored to the SRAM (the RECALL operation) from the nonvolatile memory. RECALL operations are also available under software control. For a complete list of related documentation, click here. Logic Block Diagram A5 A6 A7 A8 A9 A 11 A 12 DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 Quantum Trap 128 X 512 STORE STATIC RAM ARRAY 128 X 512 RECALL COLUMN I/O COLUMN DEC A0 A1 A2 A3 A4 A10 VCC VCAP POWER CONTROL STORE/ RECALL CONTROL HSB SOFTWARE DETECT -A0 A12 OE CE WE Cypress Semiconductor Corporation • 198 Champion Court Document Number: 001-50638 Rev. F • San Jose, CA 95134-1709 • 408-943-2600 Revised March 24, 2015 1 page STK11C68 The overall average current drawn by the STK11C68 depends on the following items: ■ The duty cycle of chip enable ■ The overall cycle rate for accesses ■ The ratio of Reads to Writes ■ CMOS versus TTL input levels ■ The operating temperature ■ The VCC level ■ I/O loading Figure 2. Current Versus Cycle Time (Read) Figure 3. Current Versus Cycle Time (Write) Best Practices nvSRAM products have been used effectively for over 15 years. While ease of use is one of the product’s main system values, experience gained working with hundreds of applications has resulted in the following suggestions as best practices: ■ The nonvolatile cells in an nvSRAM are programmed on the test floor during final test and quality assurance. Incoming inspection routines at customer or contract manufacturer’s sites sometimes reprograms these values. Final NV patterns are typically repeating patterns of AA, 55, 00, FF, A5, or 5A. The end product’s firmware should not assume that an NV array is in a set programmed state. Routines that check memory content values to determine first time system configuration, ■ cold or warm boot status, and so on must always program a unique NV pattern (for example, complex 4-byte pattern of 46 E6 49 53 hex or more random bytes) as part of the final system manufacturing test to ensure these system routines work consistently. ■ Power up boot firmware routines should rewrite the nvSRAM into the desired state. While the nvSRAM is shipped in a preset state, best practice is to again rewrite the nvSRAM into the desired state as a safeguard against events that might flip the bit inadvertently (program bugs, incoming inspection routines, and so on). Table 1. Hardware Mode Selection CE WE LH LH A12–A0 0x0000 0x1555 0x0AAA 0x1FFF 0x10F0 0x0F0F 0x0000 0x1555 0x0AAA 0x1FFF 0x10F0 0x0F0E Mode Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile STORE Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile RECALL I/O Output Data Output Data Output Data Output Data Output Data Output High Z Output Data Output Data Output Data Output Data Output Data Output High Z Notes [1] [1] Note 1. The six consecutive addresses must be in the order listed. WE must be high during all six consecutive CE controlled cycles to enable a nonvolatile cycle. Document Number: 001-50638 Rev. F Page 5 of 18 5 Page STK11C68 Software Controlled STORE/RECALL Cycle The software controlled STORE/RECALL cycle follows. [10, 11] Parameter Alt tRC tSA[10] tCW[10] tHACE[10] tRECALL[10] tAVAV tAVEL tELEH tELAX Description STORE/RECALL Initiation Cycle Time Address Setup Time Clock Pulse Width Address Hold Time RECALL Duration 25 ns Min Max 25 0 20 20 20 35 ns Min Max 35 0 25 20 20 Switching Waveform Figure 10. CE Controlled Software STORE/RECALL Cycle [11] 45 ns Min Max 45 0 30 20 20 Unit ns ns ns ns s ADDRESS CE OE tRC ADDRESS # 1 t tSA SCE tHACE DQ (DATA) DATA VALID tRC ADDRESS # 6 t / tSTORE RECALL HIGH IMPEDANCE DATA VALID Notes 10. The software sequence is clocked on the falling edge of CE without involving OE (double clocking aborts the sequence). 11. The six consecutive addresses must be read in the order listed in Table 1 on page 5. WE must be HIGH during all six consecutive cycles. Document Number: 001-50638 Rev. *F Page 11 of 18 11 Page

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