|
|
PDF CY7C1062GE Data sheet ( Hoja de datos )
| Número de pieza | CY7C1062GE | |
| Descripción | 16-Mbit (512 K words x 32 bits) Static RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de CY7C1062GE (archivo pdf) en la parte inferior de esta página. Total 20 Páginas | ||
|
No Preview Available !
CY7C1062G
CY7C1062GE
16-Mbit (512 K words × 32 bits) Static RAM
with Error-Correcting Code (ECC)
16-Mbit (512 K words × 32 bits) Static RAM with Error-Correcting Code (ECC)
Features
■ High speed
❐ tAA = 10 ns/15 ns
■ Embedded error-correcting code (ECC) for single-bit error
correction
■ Low active and standby current
❐ ICC = 90 mA typical
❐ ISB2 = 20 mA typical
■ Operating voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V
■ 1.0-V data retention
■ Automatic power-down when deselected
■ Transistor-transistor logic (TTL) compatible inputs and outputs
■ ERR pin to indicate 1-bit error detection and correction
■ Available in Pb-free 119-ball plastic ball grid array (PBGA)
package
Functional Description
CY7C1062G and CY7C1062GE are high-performance CMOS
fast static RAM devices with embedded ECC. Both have three
chip enables, giving easy memory expansion features. The
CY7C1062GE device includes an error indication pin that signals
the host processor in the case of a single bit error-detection and
correction event.
To write to the device, take Chip Enables (CE1, CE2, and CE3
LOW) and Write Enable (WE) input LOW. If Byte Enable A (BA)
is LOW, then data from I/O pins (I/O0 through I/O7) is written into
the location specified on the address pins (A0 through A18). If
Byte Enable B (BB) is LOW, then data from I/O pins (I/O8 through
I/O15) is written into the location specified on the address pins
(A0 through A18). Likewise, BC and BD correspond with the I/O
pins I/O16 to I/O23 and I/O24 to I/O31, respectively.
To read from the device, take Chip Enables (CE1, CE2, and CE3
LOW) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If the first BA is LOW, then data from the
memory location specified by the address pins appear on I/O0 to
I/O7. If BB is LOW, then data from memory appears on I/O8 to
I/O15. Likewise, BC and BD correspond to the third and fourth
bytes. See Truth Table – CY7C1062G/CY7C1062GE on page 15
for a complete description of read and write modes.
The input and output pins (I/O0 through I/O31) are placed in a
high-impedance state when the device is deselected (CE1, CE2,
or CE3 HIGH), the outputs are disabled (OE HIGH), the byte
selects are disabled (BA-D HIGH), or during a write operation
(CE1, CE2 and CE3 LOW and WE LOW).
On the CY7C1062GE device, the detection and correction of a
single-bit error in the accessed location is indicated by the
assertion of the ERR output (ERR = High)[1].
CY7C1062G and CY7C1062GE devices are available in Pb-free
119-ball plastic ball grid array (PBGA) package.
For a complete list of related documentation, click here.
Note
1. This device does not support automatic write-back on error detection.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-81609 Rev. *F
• San Jose, CA 95134-1709 • 408-943-2600
Revised September 13, 2016
1 page  
CY7C1062G
CY7C1062GE
Product Portfolio
Product
Features and Options
(see Pin Configurations
on page 4)
CY7C1062G18 Embedded ECC. No ERR
CY7C1062G30 output pin
CY7C1062GE18 Embedded ECC. Optional
CY7C1062GE30 ERR output pin
Range
Industrial
VCC Range (V)
Speed
(ns)
1.65 V–2.2 V
2.2 V–3.6 V
1.65 V–2.2 V
2.2 V–3.6 V
15
10
15
10
Power Dissipation
Operating ICC, (mA)
f = fmax
Typ [4]
Max
Standby, ISB2 (mA)
Typ [4]
Max
70 80
90 110
20 30
70 80
90 110
Notes
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 1.8 V (for VCC range of 1.65 V–2.2 V), VCC = 3 V
and (for VCC range of 2.2 V–3.6 V), TA = 25 °C.
Document Number: 001-81609 Rev. *F
Page 5 of 20
5 Page 
Switching Waveforms (continued)
Figure 7. Read Cycle No. 2 (OE Controlled) [23, 24, 25]
CY7C1062G
CY7C1062GE
ADDRESS
CE
tACE
tRC
OE
BA-D
DATA I/O
VCC
SUPPLY
CURRENT
tDOE
tLZOE
tDBE
tLZBE
HIGH IMPEDANCE
tLZCE
tPU
tPD
tHZCE
tHZOE
DATAOUT VALID
tHZBE
HIGH
IMPEDANCE
ISB
Notes
23.
CE indicates
HIGH.
a
combination
of
all
three
chip
enables.
When
active
LOW,
CE
indicates
the
CE1
,
CE2
,and
CE3
LOW.
When
HIGH,
CE
indicates
the
CE1,
CE2,
or
CE3
24. WE is HIGH for read cycle.
25. Address valid before or similar to CE transition LOW.
Document Number: 001-81609 Rev. *F
Page 11 of 20
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet CY7C1062GE.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| CY7C1062G | 16-Mbit (512 K words x 32 bits) Static RAM | Cypress Semiconductor |
| CY7C1062GE | 16-Mbit (512 K words x 32 bits) Static RAM | Cypress Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |