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PDF S70GL02GP Data sheet ( Hoja de datos )
| Número de pieza | S70GL02GP | |
| Descripción | 2 Gbit / 3V Page Mode S70GL-P MirrorBit Flash | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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S70GL02GP
2 Gbit, 3V Page Mode
S70GL-P MirrorBit® Flash
General Description
The Cypress S70GL02GP 2 Gbit Mirrorbit Flash device is fabricated on 90-nm process technology. This device offers a fast page
access time of 25 ns with a corresponding random access time of 110 ns. It features a Write Buffer that allows a maximum of 32
words/64 bytes to be programmed in one operation, resulting in faster effective programming time than standard single byte/word
programming algorithms. This makes the device an ideal product for today’s embedded applications that require higher density,
better performance and lower power consumption.
This document contains information for the S70GL02GP device, which is a dual die stack of two S29GL01GP die. For detailed
specifications, refer to the discrete die datasheet provided in Table 1.
Table 1. Affected Documents/Related Documents
Title
S29GL01GP, S29GL512P, S29GL256P, S29GL128P
1 Gbit, 512, 256, 128 Mbit, 3 V, Page Flash with 90 nm MirrorBit
Process Technology
Publication Number
002-00886
Distinctive Characteristics
Two 1024 Mbit (S29GL01GP) in a single 64-ball Fortified-
BGA package (see S29GL01P datasheet for full
specifications)
Single 3V read/program/erase (3.0V - 3.6V)
90 nm MirrorBit process technology
8-word/16-byte page read buffer
32-word/64-byte write buffer reduces overall programming
time for multiple-word writes
Secured Silicon Sector region
– 128-word/256-byte sector for permanent, secure
identification through an 8-word/16-byte random Electronic
Serial Number
– Can be programmed and locked at the factory or by the
customer
Uniform 64Kword/128KByte Sector Architecture
– S70GL02GP: two thousand forty-eight sectors
100,000 erase cycles per sector typical
20-year data retention typical
Offered Packages
– 64-ball Fortified BGA
Suspend and Resume commands for Program and Erase
operations
Write operation status bits indicate program and erase
operation completion
Unlock Bypass Program command to reduce programming
time
Support for Common Flash Interface (CFI)
Persistent and Password methods of Advanced Sector
Protection
WP#/ACC input
– Accelerates programming time (when VACC is applied) for
greater throughput during system production
– Protects first or last sector of each die, regardless of sector
protection settings
Hardware reset input (RESET#) resets device
Ready/Busy# output (RY/BY#) detects program or erase
cycle completion
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 002-01338 Rev. *D
• San Jose, CA 95134-1709 • 408-943-2600
Revised March 16, 2016
1 page  
S70GL02GP
2. Input/Output Description and Logic Symbol
Table 1 identifies the input and output package connections provided on the device.
Table 1. Input/Output Description
Symbol
A26–A0
DQ14–DQ0
DQ15/A-1
CE#
OE#
WE#
VCC
VIO
VSS
RY/BY#
BYTE#
RESET#
WP#/ACC
NC
Type
Input
I/O
I/O
Input
Input
Input
Supply
Supply
Supply
Output
Input
Input
Input
No Connect
Description
Address lines for GL02GP
Data input/output.
DQ15: Data input/output in word mode.
A-1: LSB address input in byte mode.
Chip Enable.
Output Enable.
Write Enable.
Device Power Supply.
Versatile IO Input.
Ground.
Ready/Busy. Indicates whether an Embedded Algorithm is in progress or complete. At VIL, the
device is actively erasing or programming. At High Z, the device is in ready.
Selects data bus width. At VIL, the device is in byte configuration and data I/O pins DQ0-DQ7 are
active. At VIH, the device is in word configuration and data I/O pins DQ0-DQ15 are active.
Hardware Reset. Low = device resets and returns to reading array data.
Write Protect/Acceleration Input. At VIL, disables program and erase functions in the outermost
sectors. At VHH, accelerates programming; automatically places device in unlock bypass mode.
Should be at VIH for all other conditions.
Not connected internally.
Document Number: 002-01338 Rev. *D
Page 5 of 11
5 Page 
S70GL02GP
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© Cypress Semiconductor Corporation 2006-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you under its copyright rights in the Software, a personal, non-exclusive, nontransferable license (without the right to sublicense) (a) for Software provided in source code form, to modify
and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either
directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units. Cypress also grants you a personal, non-exclusive, nontransferable, license (without the right
to sublicense) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely to the minimum
extent that is necessary for you to exercise your rights under the copyright license granted in the previous sentence. Any other use, reproduction, modification, translation, or compilation of the Software
is prohibited.
CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes to this document without further notice. Cypress does not
assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or
programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application
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hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any
component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole
or in part, and Company shall and hereby does release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. Company shall indemnify
and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress
products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United
States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 002-01338 Rev. *D
Revised March 16, 2016
Page 11 of 11
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| PDF Descargar | [ Datasheet S70GL02GP.PDF ] | |
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