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AD9278 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD9278
Beschreibung Octal LNA/VGA/AAF/ADC and CW I/Q Demodulator
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD9278 Datasheet, Funktion
Data Sheet
Octal LNA/VGA/AAF/ADC
and CW I/Q Demodulator
AD9278
FEATURES
8 channels of LNA, VGA, AAF, ADC, and I/Q demodulator
Low power: 88 mW per channel, TGC mode, 40 MSPS;
32 mW per channel, CW mode
10 mm × 10 mm, 144-ball CSP-BGA
TGC channel input-referred noise: 1.3 nV/Hz, max gain
Flexible power-down modes
Fast recovery from low power standby mode: <2 μs
Overload recovery: <10 ns
Low noise preamplifier (LNA)
Input-referred noise: 1.25 nV/√Hz, gain = 21.3 dB
Programmable gain: 15.6 dB/17.9 dB/21.3 dB
0.1 dB compression: 1000 mV p-p/
750 mV p-p/450 mV p-p
Dual-mode active input impedance matching
Bandwidth (BW): >50 MHz
Variable gain amplifier (VGA)
Attenuator range: −45 dB to 0 dB
Postamp gain (PGA): 21 dB/24 dB/27 dB/30 dB
Linear-in-dB gain control
Antialiasing filter (AAF)
Programmable second-order LPF from 8 MHz to 18 MHz
Programmable HPF
Analog-to-digital converter (ADC)
SNR: 70 dB, 12 bits up to 65 MSPS
Serial LVDS (ANSI-644, low power/reduced signal)
CW mode I/Q demodulator
Individual programmable phase rotation
Output dynamic range per channel: >158 dBc/√Hz
Output-referred SNR: 153 dBc/√Hz, 1 kHz offset, −3 dBFS
GENERAL DESCRIPTION
The AD9278 is designed for low cost, low power, small size,
and ease of use for medical ultrasound and automotive radar. It
contains eight channels of a variable gain amplifier (VGA) with
a low noise preamplifier (LNA), an antialiasing filter (AAF), an
analog-to-digital converter (ADC), and an I/Q demodulator
with programmable phase rotation.
Each channel features a variable gain range of 45 dB, a fully
differential signal path, an active input preamplifier termination,
and a maximum gain of up to 51 dB. The channel is optimized
for high dynamic performance and low power in applications
where a small package size is critical.
The LNA has a single-ended-to-differential gain that is selectable
through the SPI. Assuming a 15 MHz noise bandwidth (NBW)
and a 21.3 dB LNA gain, the LNA input SNR is roughly 88 dB.
In CW Doppler mode, each LNA output drives an I/Q demod-
ulator that has independently programmable phase rotation
with 16 phase settings.
Power-down of individual channels is supported to increase
battery life for portable applications. Standby mode allows quick
power-up for power cycling. In CW Doppler operation, the
VGA, AAF, and ADC are powered down. The ADC contains
several features designed to maximize flexibility and minimize
system cost, such as a programmable clock, data alignment, and
programmable digital test pattern generation. The digital test
patterns include built-in fixed patterns, built-in pseudo random
patterns, and custom user-defined test patterns entered via the
serial port interface.
FUNCTIONAL BLOCK DIAGRAM
AVDD1 AVDD2 PDWN STBY
DRVDD
LO-A TO LO-H
LOSW-A TO LOSW-H
LI-A TO LI-H
LG-A TO LG-H
LNA
I/Q
DEMODULATOR
VGA
AAF
8 CHANNELS
12-BIT
ADC
SERIAL
LVDS
DOUTA+ TO DOUTH+
DOUTA– TO DOUTH–
LO
GENERATION
REFERENCE
SERIAL
PORT
INTERFACE
DATA
RATE
MULTIPLIER
FCO+
FCO–
DCO+
DCO–
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2010–2012 Analog Devices, Inc. All rights reserved.






AD9278 Datasheet, Funktion
Data Sheet
AD9278
Parameter1
Input-Referred Noise Voltage
Noise Figure
Input-Referred Dynamic Range
Output-Referred SNR
Two-Tone Intermodulation (IMD3)
Quadrature Phase Error
I/Q Amplitude Imbalance
Channel-to-Channel Matching
POWER SUPPLY, MODE I/II/III/IV
AVDD1
AVDD23
DRVDD
IAVDD1
Test Conditions/Comments
RS = 0 Ω, RFB = ∞
LNA gain = 15.6 dB
LNA gain = 17.9 dB
LNA gain = 21.3 dB
RS = 50 Ω, RFB = ∞
LNA gain = 15.6 dB
LNA gain = 17.9 dB
LNA gain = 21.3 dB
RS = 0 Ω, RFB = ∞
LNA gain = 15.6 dB
LNA gain = 17.9 dB
LNA gain = 21.3 dB
−3 dBFS input, fRF = 2.5 MHz, f4LO =
10 MHz, 1 kHz offset
fRF1 = 5.015 MHz, fRF2 = 5.020 MHz,
f4LO = 20 MHz, ARF1 = −1 dBFS, ARF2 =
−21 dBFS, IMD3 relative to ARF2
I to Q, all phases, 1 σ
I to Q, all phases, 1 σ
Phase I to I, Q to Q, 1 σ
Amplitude I to I, Q to Q, 1 σ
TGC mode
IAVDD2
IDRVDD
Total Power Dissipation
(Including Output Drivers)
Power-Down Dissipation
Standby Power Dissipation
Power Supply Rejection Ratio
(PSRR)
ADC RESOLUTION
ADC REFERENCE
Output Voltage Error
Load Regulation at 1.0 mA
Input Resistance
CW Doppler mode
TGC mode, no signal
CW Doppler mode
ANSI-644 mode
Low power (IEEE 1596.3 similar) mode
TGC mode, no signal
CW Doppler mode
VREF = 1 V
VREF = 1 V
Min
1.7
2.7
1.7
Typ Max Unit
2.0 nV/√Hz
1.9 nV/√Hz
1.8 nV/√Hz
7.8 dB
7.3 dB
6.9 dB
162 dBFS/√Hz
160 dBFS/√Hz
157 dBFS/√Hz
153 dBc/√Hz
−58 dB
0.15
0.015
0.5
0.25
1.8
3.0
1.8
178/145/
215/260
32
108
63
47/44/48/53
33/31/34/38
704/640/
772/860
252
420
1.6
12
1.9
3.6
1.9
815/755/
908/996
5
±50
2
6
Degrees
dB
Degrees
dB
V
V
V
mA
mA
mA
mA
mA
mW
mW
mW
mW
mV/V
Bits
mV
mV
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and information about how these tests were completed.
2 The overrange condition is specified as 6 dB more than the full-scale input range.
3 When the LNA gain is set to 15.6 dB, AVDD2 >3.0 V.
Rev. A | Page 5 of 44

6 Page









AD9278 pdf, datenblatt
Data Sheet
Table 6. Pin Function Descriptions
Pin No.
B5, B6, B8, C5, C6, C7, C8, D5, D6, D7, D8,
E1, E5, E6, E7, E8, E12, F2, F4, F6, F7, F9,
F11, G1, G3, G5, G6, G7, G8, G10, G12,
H2, H3, H4, H5, H6, H7, H8, H9, H10, H11,
J2, J4, J8, K1, K2, K4, M1, M12
F1, F3, F5, F8, F10, F12, G2, G4, G9, G11
B7, E2, E3, E4, E9, E10, E11, J6, K6
L1, L12
A1
B1
C2
D2
A2
B2
C3
D3
A3
B3
C4
D4
A4
B4
H1
J1
M2
L2
M3
L3
M4
L4
M5
L5
M6
L6
M7
L7
M8
L8
M9
L9
M10
L10
M11
L11
K11
J11
K12
J12
H12
B9
A9
D9
C9
Name
GND
AVDD1
AVDD2
DRVDD
LI-E
LG-E
LO-F
LOSW-F
LI-F
LG-F
LO-G
LOSW-G
LI-G
LG-G
LO-H
LOSW-H
LI-H
LG-H
CLK−
CLK+
DOUTH−
DOUTH+
DOUTG−
DOUTG+
DOUTF−
DOUTF+
DOUTE−
DOUTE+
DCO−
DCO+
FCO−
FCO+
DOUTD−
DOUTD+
DOUTC−
DOUTC+
DOUTB−
DOUTB+
DOUTA−
DOUTA+
STBY
PDWN
SCLK
SDIO
CSB
LG-A
LI-A
LOSW-A
LO-A
Description
Ground (should be tied to a quiet analog ground)
1.8 V Analog Supply
3.0 V Analog Supply
1.8 V Digital Output Driver Supply
LNA Analog Input for Channel E
LNA Ground for Channel E
LNA Analog Inverted Output for Channel F
LNA Analog Switched Output for Channel F
LNA Analog Input for Channel F
LNA Ground for Channel F
LNA Analog Inverted Output for Channel G
LNA Analog Switched Output for Channel G
LNA Analog Input for Channel G
LNA Ground for Channel G
LNA Analog Inverted Output for Channel H
LNA Analog Switched Output for Channel H
LNA Analog Input for Channel H
LNA Ground for Channel H
Clock Input Complement
Clock Input True
ADC H Digital Output Complement
ADC H Digital Output True
ADC G Digital Output Complement
ADC G Digital Output True
ADC F Digital Output Complement
ADC F Digital Output True
ADC E Digital Output Complement
ADC E Digital Output True
Digital Clock Output Complement
Digital Clock Output True
Frame Clock Digital Output Complement
Frame Clock Digital Output True
ADC D Digital Output Complement
ADC D Digital Output True
ADC C Digital Output Complement
ADC C Digital Output True
ADC B Digital Output Complement
ADC B Digital Output True
ADC A Digital Output Complement
ADC A Digital Output True
Standby Power-Down
Full Power-Down
Serial Clock
Serial Data Input/Output
Chip Select Bar
LNA Ground for Channel A
LNA Analog Input for Channel A
LNA Analog Switched Output for Channel A
LNA Analog Inverted Output for Channel A
Rev. A | Page 11 of 44
AD9278

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