PDF ADF4196 Data sheet ( Hoja de datos )

Número de pieza	ADF4196
Descripción	6 GHz PLL Frequency Synthesizer
Fabricantes	Analog Devices
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No Preview Available ! Data Sheet Low Phase Noise, Fast Settling, 6 GHz PLL Frequency Synthesizer ADF4196 FEATURES Fast settling, fractional-N PLL architecture Single PLL replaces ping-pong synthesizers Frequency hop across GSM band in 5 μs with phase settled within 20 μs 1 degree rms phase error at 4 GHz RF output Digitally programmable output phase RF input range up to 6 GHz 3-wire serial interface On-chip, low noise differential amplifier Phase noise figure of merit: −216 dBc/Hz APPLICATIONS GSM/EDGE base stations PHS base stations Pulse Doppler radar Instrumentation and test equipment Beam-forming/phased array systems GENERAL DESCRIPTION The ADF4196 frequency synthesizer can be used to implement local oscillators (LO) in the upconversion and downconversion sections of wireless receivers and transmitters. Its architecture is specifically designed to meet the GSM/EDGE lock time require- ments for base stations, and the fast settling feature makes the ADF4196 suitable for pulse Doppler radar applications. The ADF4196 consists of a low noise, digital phase frequency detector (PFD) and a precision differential charge pump. A differential amplifier converts the differential charge pump output to a single-ended voltage for the external voltage controlled oscillator (VCO). The sigma-delta (Σ-Δ) based fractional inter- polator, working with the N divider, allows programmable modulus fractional-N division. Additionally, the 4-bit reference (R) counter and on-chip frequency doubler allow selectable reference signal (REFIN) frequencies at the PFD input. A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and a VCO. The switching architecture ensures that the PLL settles within the GSM time slot guard period, removing the need for a second PLL and associated isolation switches. This decreases the cost, complexity, PCB area, shielding, and characterization found on previous ping-pong GSM PLL architectures. FUNCTIONAL BLOCK DIAGRAM SDVDD DVDD1 DVDD2 DVDD3 AVDD VP1 VP2 VP3 RSET REFIN MUXOUT CLK DATA LE ×2 DOUBLER HIGH-Z OUTPUT MUX 24-BIT DATA REGISTER 4-BIT R COUNTER /2 DIVIDER VDD DGND LOCK DETECT RDIV NDIV FRACTIONAL INTERPOLATOR REFERENCE + PHASE FREQUENCY – DETECTOR CHARGE + PUMP – DIFFERENTIAL AMPLIFIER – + N COUNTER FRACTION MODULUS REG REG INTEGER REG ADF4196 SW1 CPOUT+ CPOUT– SW2 CMR AIN– AIN+ AOUT SW3 RFIN+ RFIN– AGND1 AGND2 DGND1 DGND2 Figure 1. DGND3 SDGND SWGND Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2011–2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com 1 page ADF4196 Data Sheet Parameter SW1, SW2, AND SW3 On Resistance SW1 and SW2 SW3 NOISE CHARACTERISTICS Output 900 MHz2 1800 MHz3 Phase Noise Normalized Phase Noise Floor (PNSYNTH)4 Normalized 1/f Noise (PN1_f)5 Min Typ Max 65 75 −108 −102 −216 −110 Unit Test Conditions/Comments Ω Ω dBc/Hz At 5 kHz offset and 26 MHz PFD frequency dBc/Hz At 5 kHz offset and 13 MHz PFD frequency dBc/Hz dBc/Hz At VCO output with dither off, PLL loop bandwidth = 500 kHz Measured at 10 kHz offset, normalized to 1 GHz 1 Choose a prescaler value that ensures that the frequency on the RF input is less than the maximum allowable prescaler frequency (750 MHz). 2 fREFIN = 26 MHz; fSTEP = 200 kHz; fRF = 900 MHz; loop bandwidth = 40 kHz. 3 fREFIN = 13 MHz; fSTEP = 200 kHz; fRF = 1800 MHz; loop bandwidth = 60 kHz. 4 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log(N) (where N is the N divider value) and 10 log(fPFD). PNSYNTH = PNTOT − 10 log(fPFD) − 20 log(N). 5 The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, fRF, and at an offset frequency, f, is given by PN = P1_f + 10 log(10 kHz/f) + 20 log(fRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL™. TIMING CHARACTERISTICS AVDD = DVDD1, DVDD2, DVDD3 = 3 V ± 10%; VP1, VP2 = 5 V ± 10%; VP3 = 5.35 V ± 5%; AGND1, AGND2 = DGND1, DGND2, DGND3 = 0 V; RSET = 2.4 kΩ; dBm referred to 50 Ω; TA = TMIN to TMAX, unless otherwise noted. Operating temperature = −40°C to +85°C. Table 2. Parameter t1 t2 t3 t4 t5 t6 t7 Limit 10 ns min 10 ns min 10 ns min 15 ns min 15 ns min 10 ns min 15 ns min Description LE setup time DATA to CLK setup time DATA to CLK hold time CLK high duration CLK low duration CLK to LE setup time LE pulse width Timing Diagram CLK t4 t5 t2 t3 DATA LE DB23 (MSB) DB22 DB2 (LSB) (CONTROL BIT C3) DB1 (LSB) (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1) t7 t1 t6 LE Figure 2. Timing Diagram Rev. D \| Page 4 of 28 5 Page ADF4196 1000 100 7nV/ Hz @ 20kHz 10 1 1k 10k 100k 1M FREQUENCY (Hz) Figure 16. Voltage Noise Density Measured at the Differential Amplifier Output 10M 100 90 80 SW1, SW2 +85°C 70 +25°C 60 –40°C 50 40 30 20 SW3 +85°C +25°C –40°C TUNING VOLTAGE RANGE 10 0 012345 DRAIN VOLTAGE (V) Figure 17. On Resistance of the SW1, SW2, and SW3 Loop Filter Switches Data Sheet 1.8 MEASURED USING AD8302 PHASE DETECTOR Y-AXIS SCALE: 10mV/DEGREE RF = 1880MHz, PFD = 26MHz, MOD = 130 1.5 X-AXIS SCALE: 2.77°/STEP 1.2 0.9 0.6 0.3 0 0 13 26 39 52 65 78 91 104 117 130 PHASE CODE Figure 18. Detected RF Output Phase for Phase Code Sweep from 0 to MOD 104MHz 5dBm ADF4193 EVAL BOARD REFIN RFOUT 1805MHz 1880MHz INPA SIGNAL GENERATOR 10MHz EXT REF VPHS INPB AD8302 EVB 1880MHz OSCILLOSCOPE SIGNAL GENERATOR INTERVAL BETWEEN R0 WRITES SHOULD BE A MULTIPLE OF MOD REFERENCE CYCLES (5µs) FOR COHERENT PHASE MEASUREMENTS Figure 19. Test Setup for Phase Lock Time Measurements Rev. D \| Page 10 of 28 11 Page

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