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ADF7030 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADF7030
Beschreibung Radio Transceiver IC
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 25 Seiten
ADF7030 Datasheet, Funktion
Data Sheet
High Performance, Low Power,
169 MHz ISM Band, Radio Transceiver IC
ADF7030
FEATURES
Host microprocessor interface
RF frequency range: 169.4 MHz to 169.6 MHz
Modulation: 2 Gaussian frequency key shifting (GFSK), 4GFSK
Data rates
2GFSK: 2.4 kbps and 4.8 kbps
4GFSK: 6.4 kbps (transmitter only)
Easy to use programming interface (SPI)
Configurable output and input interrupts
Suitable for systems targeting compliance with
ETSI EN 300 220
6 mm × 6 mm, 40-lead, standard lead LFCSP
Low power consumption
1 nA sleep current
Receiver (Rx) performance
97 dB blocking at ±10 MHz offset
93 dB blocking at ±2 MHz offset
66 dB adjacent channel rejection
−122.8 dBm sensitivity at BER = 0.1%
APPLICATIONS
Wireless M-Bus Mode N (EN 13757-4)
Smart metering
Social alarms
Active tag asset tracking
GENERAL DESCRIPTION
Transmitter (Tx) performance
The ADF7030 is a low power, high performance, integrated
2 power amplifier (PA) outputs
radio transceiver supporting narrow-band operation in the
−20 dBm to +17 dBm output power range
169.4 MHz to 169.6 MHz ISM band. The ADF7030 supports
0.1 dB output power step resolution
transmit and receive operation at 2.4 kbps and 4.8 kbps using
Very low output power variation vs. temperature and supply
2GFSK modulation and transmit operation at 6.4 kbps using
61 mA Tx current at 17 dBm
Accurate digital received signal strength indication (RSSI)
Fast settling automatic frequency control (AFC) algorithm for
very short preambles
Autonomous automatic gain control (AGC) algorithm
4GFSK modulation.
The ADF7030 features an on-chip ARM® Cortex®-M0 processor
that performs radio control and calibration, as well as packet
management.
On-chip ARM Cortex-M0 processor performs the following
functions:
Radio control
Radio calibration
Packet management
FUNCTIONAL BLOCK DIAGRAM
LDOx
TCXO BUFFER
LNA
RECEIVER
PA SYNTHESIZER
PA TRANSMITTER
DIGITAL
BASEBAND
ARM
CORTEX-M0
ROM
RAM
ADF7030
INTERRUPT
CONTROLLER
SPI
SLAVE
CONFIGURABLE
GPIOs
Figure 1.
Rev. 0
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Technical Support
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ADF7030 Datasheet, Funktion
Data Sheet
ADF7030
Parameter
Min Typ Max Unit Test Conditions/Comments
MAXIMUM HARMONIC EMISSIONS
Measured conductively at antenna input, according to
ETSI EN 300 220-1 V2.4.1 on the ADF7030 evaluation
board; transmitting continuous PN9 data
17 dBm Output Power
PA2
Second Harmonic
−74 dBc
Third Harmonic
−86 dBc
Fourth Harmonic
−90 dBc
All Other Harmonics
<−90
dBc
13 dBm Output Power
PA1
Second Harmonic
−73 dBc
Third Harmonic
−82 dBc
Fourth Harmonic
−90 dBc
All Other Harmonics
<−90
dBc
OPTIMUM PA LOAD IMPEDANCE
PA1
47 + j10
Ω
PA2
38 + j10
Ω
RECEIVER SPECIFICATIONS
Table 3.
Parameter
SENSITIVITY, BIT ERROR ATE (BER)
Min
2.4 kbps
4.8 kbps
SENSITIVITY, PACKET ERROR RATE (PER)
Typ
−122.8
−121.4
2.4 kbps
4.8 kbps
CHANNEL SELECTIVITY AND BLOCKING
BER-Based Test Method
−121.2
−119.5
2.4 kbps
Adjacent Channel (±12.5 kHz)
Alternate Channel (±25 kHz)
±2 MHz
±10 MHz
4.8 kbps
Adjacent Channel (±12.5 kHz)
Alternate Channel (±25 kHz)
±2 MHz
±10 MHz
66
70
93
97
63
69
93
96
Max Unit Test Conditions/Comments
At BER = 0.1%, AFC disabled, 2GFSK frequency deviation =
2.4 kHz
dBm
dBm
At PER = 5%, preamble length = 2 bytes, sync word =
0xF672, payload length = 24 bytes, data rate error
tolerance = ±400 ppm, RF frequency error range = ±2 kHz,
AFC enabled, 2GFSK frequency deviation = 2.4 kHz
dBm
dBm
Desired signal 3 dB above the input sensitivity level
(BER = 0.1%), carrier wave (CW) interferer power level
increased until BER = 0.1%, image calibrated, 12.5 kHz
channel spacing, 2GFSK frequency deviation = 2.4 kHz
dB
dB
dB
dB
dB
dB
dB
dB
Rev. 0 | Page 5 of 24

6 Page









ADF7030 pdf, datenblatt
Data Sheet
ADF7030
Pin No.
29
30
31
32
33
34
35
36
37
38
39
40
Mnemonic
GPIO6
DNC
DNC
GPIO7
DNC
CREG5
HFXTALP
HFXTALN
CREG6
CREG7
CLF
VBAT6
EPAD
Description
Digital GPIO Pin 6
Do Not Connect. Do not connect to this pin.
Do Not Connect. Do not connect to this pin.
Digital GPIO Pin 7.
Do Not Connect. Do not connect to this pin.
Regulator Output 5. Place a 220 nF capacitor between this pin and ground for regulator stability and noise rejection.
Do Not Connect. Do not connect to this pin.
Reference Input. Connect this pin to an external 26 MHz reference (typically a TCXO).
Regulator Output 6. Place a 220 nF capacitor between this pin and ground for regulator stability and noise rejection.
Regulator Output 7. Place a 220 nF capacitor between this pin and ground for regulator stability and noise rejection.
External Loop Filter Capacitor to CREG1. Place a 1.2 nF capacitor between this pin and the CREG1 pin.
Power Supply Pin 6 to the Internal Regulators.
Exposed Pad. Connect the exposed pad to ground.
Rev. 0 | Page 11 of 24

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