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PDF CAT24C01B Data sheet ( Hoja de datos )
| Número de pieza | CAT24C01B | |
| Descripción | 1K-Bit Serial EEPROM | |
| Fabricantes | Catalyst Semiconductor | |
| Logotipo |  |
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CAT24C01B
1K-Bit Serial EEPROM
FEATURES
s 2-Wire Serial Interface
s 1.8 to 6.0Volt Operation
s Low Power CMOS Technology
s 4-Byte Page Write Buffer
s Self-Timed Write Cycle with Auto-Clear
DESCRIPTION
The CAT24C01B is a 1K-bit Serial CMOS EEPROM
internally organized as 128 words of 8 bits each. Catalyst’s
advanced CMOS technology substantially reduces de-
vice power requirements. The CAT24C01B features a
PIN CONFIGURATION
DIP Package (P)
SOIC Package (J)
NC
NC
NC
VSS
1
2
3
4
8 VCC
7 TEST
6 SCL
5 SDA
NC
NC
NC
VSS
1
2
3
4
8 VCC
7 TEST
6 SCL
5 SDA
s 1,000,000 Program/Erase Cycles
s 100 Year Data Retention
s 8-pin DIP, 8-pin SOIC, 8 pin TSSOP or 8-pin MSOP
s Commercial, Industrial and Automotive
Temperature Ranges
4-byte page write buffer. The device operates via a 2-
wire serial interface and is available in 8-pin DIP, 8-pin
SOIC, 8-pin TSSOP or 8-pin MSOP.
BLOCK DIAGRAM
EXTERNAL LOAD
VCC
VSS
DOUT
ACK
WORD ADDRESS
BUFFERS
SENSE AMPS
SHIFT REGISTERS
COLUMN
DECODERS
MSOP Package (R)
NC
NC
NC
VSS
1
2
3
4
8 VCC NC
7 TEST NC
6 SCL NC
5 SDA VSS
5020 FHD F01
TSSOP Package (U)
SDA
1 8 VCC
2 7 TEST
3 6 SCL
4 5 SDA
START/STOP
LOGIC
CONTROL
LOGIC
XDEC
EEE2PPRROOMM
PIN FUNCTIONS
Pin Name
Function
NC No Connect
SDA
Serial Data/Address
SCL Serial Clock
VCC +1.8V to +6.0V Power Supply
VSS Ground
TEST
Test Input (GND, VCC or
Floating)
SCL
STATE COUNTERS
DATA IN STORAGE
HIGH VOLTAGE/
TIMING CONTROL
© 1999 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 25085-00 7/99 S-1
1 page  
CAT24C01B
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24C01B monitors the
SDA and SCL lines and will not respond until this
condition is met.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
Acknowledge
After a successful data transfer, each receiving device is
required to generate an acknowledge. The Acknowledg-
ing device pulls down the SDA line during the ninth clock
cycle, signaling that it received the 8 bits of data.
The CAT24C01B responds with an acknowledge after
receiving a START condition and its word address. If the
device has been selected along with a write operation,
it responds with an acknowledge after receiving each 8-
bit byte.
When the CAT24C01B is in a READ mode it transmits
8 bits of data, releases the SDA line, and monitors the
line for an acknowledge. Once it receives this acknowl-
edge, the CAT24C01B will continue to transmit data. If
no acknowledge is sent by the Master, the device
terminates data transmission and waits for a STOP
condition.
WRITE OPERATIONS
Byte Write
In the Byte Write mode, the Master device sends the
START condition and the word address information
Figure 4. Acknowledge Timing
(with the R/W bit set to zero) to the Slave device. After the
Slave generates an acknowledge, the Master device
transmits the data byte to be written into the addressed
memory location. The CAT24C01B acknowledge once
more and the Master generates the STOP condition, at
which time the device begins its internal programming
cycle to nonvolatile memory. While this internal cycle is
in progress, the device will not respond to any request
from the Master device.
Page Write
The CAT24C01B writes up to 4 bytes of data in a single
write cycle, using the Page Write operation. The Page
Write operation is initiated in the same manner as the
Byte Write operation, however instead of terminating
after the initial word is transmitted, the Master is allowed
to send up to 3 additional bytes. After each byte has been
transmitted the CAT24C01B will respond with an ac-
knowledge, and internally increment the low order ad-
dress bits by one. The high order bits remain un-
changed.
If the Master transmits more than 4 bytes prior to sending
the STOP condition, the address counter ‘wraps around,’
and previously transmitted data will be overwritten.
Once all 4 bytes are received and the STOP condition
has been sent by the Master, the internal programming
cycle begins. At this point all received data is written to
the CAT24C01B in a single write cycle.
Acknowledge Polling
The disabling of the inputs can be used to take advan-
SCL FROM
MASTER
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
1
5
89
ACKNOWLEDGE
5020 FHD F06
Doc. No. 25085-00 7/99 S-1
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet CAT24C01B.PDF ] | |
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