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ADP1052 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADP1052
Beschreibung Digital Controller for Isolated Power Supply
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
ADP1052 Datasheet, Funktion
Data Sheet
Digital Controller for Isolated
Power Supply with PMBus Interface
ADP1052
FEATURES
GENERAL DESCRIPTION
Peak data telemetry recording
The ADP1052 is an advanced digital controller with a PMBus™
High speed input voltage feedforward control
interface targeting high density, high efficiency, dc-to-dc power
6 pulse-width modulation (PWM) logic outputs with 625 ps
conversion. This controller implements voltage mode control with
resolution
high speed, input line feedforward for enhanced transient and
Switching frequency: 49 kHz to 625 kHz
improved noise performance. The ADP1052 has six programmable
Frequency synchronization as master and slave device
pulse-width modulation (PWM) outputs capable of controlling
Multiple energy saving modes
most high efficiency power supply topologies, with added control
Adaptive dead time compensation for efficiency optimization
of synchronous rectification (SR). The device includes adaptive
Low power consumption: 100 mW typical
dead time compensation to improve efficiency over the load range,
Direct parallel control for power supplies without OR’ing devices
and programmable light load mode operation, combined with
Accurate droop current share
low power consumption, to reduce system standby power losses.
Prebias startup
Reverse current protection
Conditional overvoltage protection
Extensive fault detection and protection
PMBus compliant
Graphical user interface (GUI) for ease of programming
On-board EEPROM for programming and data storage
Available in a 24-lead, 4 mm × 4 mm LFCSP
The ADP1052 implements several features to enable a robust
system of parallel and redundant operation for customers that
require high availability or parallel connection. The device provides
synchronization, reverse current protection, prebias startup,
accurate current sharing between power supplies, and conditional
overvoltage techniques to identify and safely shut down an
erroneous power supply in parallel operation mode.
−40°C to +125°C operating temperature
The ADP1052 is based on flexible state machine architecture
APPLICATIONS
and is programmed using an intuitive GUI. The easy to use
interface reduces design cycle time and results in a robust,
High density isolated dc-to-dc power supplies
hardware coded system loaded into the built-in EEPROM. The
Intermediate bus converters
small size (4 mm × 4 mm) LFCSP package makes the ADP1052
High availability parallel power systems
ideal for ultracompact, isolated dc-to-dc power module or
Server, storage, industrial, networking, and communications
embedded power designs.
infrastructure
TYPICAL APPLICATIONS CIRCUIT
DC
INPUT
LOAD
DRIVER
iCoupler®
DRIVER
SR1 SR2
CS1
OUTA
OUTB
OUTC
OUTD
RES ADD RTD VCORE
VF CS2– CS2+ OVP VS+ VS–
ADP1052
SYNI/FLGI
VDD
PG/ALT CTRL SDA SCL AGND
PMBus
Figure 1.
Rev. A
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Tel: 781.329.4700
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Technical Support
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ADP1052 Datasheet, Funktion
Data Sheet
ADP1052
Parameter
VS High Speed ADC
Equivalent Sampling Frequency
Equivalent Resolution
Dynamic Range
VS Undervoltage Protection (UVP) Digital
Comparator
Threshold Accuracy
Comparator Update Speed
OVP PIN
Leakage Current
Overvoltage Protection (OVP) Comparator
Voltage Range
Threshold Accuracy
Propagation Delay (Latency)
VF VOLTAGE SENSE PIN
Input Voltage Range
Leakage Current
General ADC
Valid Input Voltage Range
ADC Clock Frequency
Register Update Rate
Measurement
Resolution
Accuracy
Feedforward Voltage (VF) UVP Digital
Comparator
Threshold Accuracy
Symbol
fSAMP
VIN
Min
−2
0.75
−1.6
0
0
−2
−32
−5
−80
Typ Max Unit
fSW kHz
6 Bits
±25 mV
+2 % FSR
82 µs
1.0 µA
1.5 V
1 +1.6 %
61 85 ns
1 1.6 V
1.0 µA
1.6 V
1.56 MHz
1.31 ms
11 Bits
+2 % FSR
+32 mV
+5 % FSR
+80 mV
Comparator Update Speed
Feedforward ADC
Input Voltage Range
Resolution
Sampling Period
CS1 CURRENT SENSE PIN
Input Voltage Range
Source Current
CS1 ADC
Valid Input Voltage Range
ADC Clock Frequency
Register Update Rate
Measurement
Resolution
Accuracy
CS1 Overcurrent Protection (OCP)
Comparator
Reference Accuracy
Propagation Delay (Latency)
1.31 ms
VIN 0.5
1 1.6 V
11 Bits
10 μs
VIN 0
1
−1.2
1.6 V
−0.35 µA
0 1.6 V
1.56 MHz
10 ms
12 Bits
−2 +2 % FSR
−32 +32 mV
−5 +5 % FSR
−80 +80 mV
1.185
0.235
1.2 1.215
0.25 0.265
65 105
Rev. A | Page 5 of 113
V
V
ns
Test Conditions/Comments
fSW = 390.5 kHz
Regulation voltage = 0 mV to 1.6 V
Triggers VOUT_UV_FAULT flag
10% to 90% of input voltage range
Triggers VOUT_OV_FAULT flag
Differential voltage from OVP to VS−
0.75 V to 1.5 V voltage range
Debounce time not included
Voltage from VF to AGND
10% to 90% of input voltage range
0% to 100% of input voltage range
Triggers VIN_LOW or VIN_UV_FAULT flag
Based on VF general ADC parameter
values
Voltage from CS1 to AGND
10% to 90% of input voltage range
0% to 100% of input voltage range
Triggers internal CS1_OCP flag
When set to 1.2 V
When set to 0.25 V
Debounce/blanking time not included

6 Page









ADP1052 pdf, datenblatt
Data Sheet
ADP1052
Pin No. Mnemonic
17 PG/ALT
18 VCORE
19 VDD
20 AGND
21 RES
22 ADD
23 RTD
24 OVP
EP
Description
Power-Good Output (Open-Drain). Connect this pin to VDD through a pull-up resistor (typically 2.2 kΩ). This
signal is referred to AGND. This pin is also used as an SMBus ALERT signal. (For information about the SMBus
specification, see the PMBus Features section.)
Output of the 2.6 V Regulator. Connect a decoupling capacitor of at least 330 nF from this pin to AGND, as close
as possible to the ADP1052, minimizing the printed circuit board (PCB) trace length. It is recommended that this
pin not be used as a reference or to generate other logic levels using resistive dividers.
Positive Supply Input. Voltage of 3.0 V to 3.6 V. This signal is referred to AGND. Connect a 2.2 μF decoupling
capacitor from this pin to AGND, as close as possible to the ADP1052, minimizing the PCB trace length.
Common Analog Ground. The internal analog circuitry ground and digital circuitry ground are star connected to
this pin through bonding wires.
Resistor Input. This pin sets up the internal reference for the internal PLL frequency. Connect a 10 kΩ resistor
(±0.1%) from this pin to AGND. This signal is referred to AGND.
Address Select Input. This pin programs the I2C/PMBus address. Connect a resistor from ADD to AGND. This signal
is referred to AGND.
Thermistor Input. Place a thermistor (R25 = 100 kΩ (1%), beta = 4250 (1%)) in parallel with a 16.5 kΩ (1%) resistor
and a 1 nF filtering capacitor. This pin is referred to AGND. When not in use, connect this pin to AGND.
Overvoltage Protection. Use this signal for redundant overvoltage protection. This signal is referred to AGND.
Exposed Pad. The ADP1052 has an exposed thermal pad on the underside of the package. For increased
reliability of the solder joints and maximum thermal capability, it is recommended that the exposed pad be
soldered to the PCB AGND plane.
Rev. A | Page 11 of 113

12 Page





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