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AD5420 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD5420
Beschreibung Current Source DAC
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD5420 Datasheet, Funktion
Data Sheet
Single-Channel, 12-/16-Bit, Serial Input, 4 mA to
20 mA, Current Source DAC, HART Connectivity
AD5410/AD5420
FEATURES
12-/16-bit resolution and monotonicity
Current output ranges: 4 mA to 20 mA, 0 mA to 20 mA, or
0 mA to 24 mA
±0.01% FSR typical total unadjusted error (TUE)
±3 ppm/°C typical output drift
Flexible serial digital interface
On-chip output fault detection
On-chip reference (10 ppm/°C maximum)
Feedback/monitoring of output current
Asynchronous clear function
Power supply (AVDD) range
10.8 V to 40 V; AD5410AREZ/AD5420AREZ
10.8 V to 60 V; AD5410ACPZ/AD5420ACPZ
Output loop compliance to AVDD − 2.5 V
Temperature range: −40°C to +85°C
24-lead TSSOP and 40-lead LFCSP packages
APPLICATIONS
Process control
Actuator control
PLC
HART network connectivity
GENERAL DESCRIPTION
The AD5410/AD5420 are low cost, precision, fully integrated
12-/16-bit converters offering a programmable current source
output designed to meet the requirements of industrial process
control applications. The output current range is programmable
at 4 mA to 20 mA, 0 mA to 20 mA, or an overrange function of
0 mA to 24 mA. The output is open-circuit protected. The device
operates with a power supply (AVDD) range from 10.8 V to
60 V. Output loop compliance is 0 V to AVDD − 2.5 V.
The flexible serial interface is SPI, MICROWIRE™, QSPI™, and
DSP compatible and can be operated in 3-wire mode to mini-
mize the digital isolation required in isolated applications.
The device also includes a power-on reset function, ensuring
that the device powers up in a known state, and an asynchronous
CLEAR pin that sets the output to the low end of the selected
current range.
The total unadjusted error is typically ±0.01% FSR.
COMPANION PRODUCTS
HART Modem: AD5700, AD5700-1
DVCC
SELECT
FUNCTIONAL BLOCK DIAGRAM
DVCC
CAP1
CAP2
AV DD
CLEAR
AD5410/AD5420
R3SENSE
R2 R3
BOOST
LATCH
SCLK
SDIN
SDO
INPUT SHIFT
REGISTER
AND CONTROL
LOGIC
12/16
12-/16-BIT
DAC
POWER-
ON
RESET
VREF
RSET
IOUT
FAULT
RSET
REFOUT
REFIN
Figure 1.
GND
Rev. H
Document Feedback
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responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2009–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com






AD5420 Datasheet, Funktion
AD5410/AD5420
Data Sheet
AC PERFORMANCE CHARACTERISTICS
AVDD = 10.8 V to 26.4 V, GND = 0 V, REFIN = 5 V external; DVCC = 2.7 V to 5.5 V, RLOAD = 300 Ω; all specifications TMIN to TMAX, unless
otherwise noted.
Table 2.
Parameter1
Min Typ Max Unit Test Conditions/Comments
DYNAMIC PERFORMANCE
Output Current Settling Time2
10
µs 16 mA step, to 0.1% FSR
40 µs 16 mA step, to 0.1% FSR, L = 1 mH
AC PSRR
−75 dB 200 mV, 50 Hz/60 Hz sine wave superimposed on power supply voltage
1 Guaranteed by design and characterization; not production tested.
2 Digital slew rate control feature disabled and CAP1 = CAP2 = open circuit.
TIMING CHARACTERISTICS
AVDD = 10.8 V to 26.4 V, GND = 0 V, REFIN = 5 V external; DVCC = 2.7 V to 5.5 V, RLOAD = 300 Ω; all specifications TMIN to TMAX, unless
otherwise noted.
Table 3.
Parameter1, 2, 3
WRITE MODE
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
READBACK MODE
t11
t12
t13
t14
t15
t16
t17
t18
t19
t20
DAISY-CHAIN MODE
t21
t22
t23
t24
t25
t26
t27
t28
t29
Limit at TMIN, TMAX
33
13
13
13
5
5
5
40
20
5
90
40
40
13
40
5
5
40
35
35
90
40
40
13
40
5
5
40
35
Unit
ns min
ns min
ns min
ns min
µs min
ns min
ns min
ns min
ns min
µs max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
Description
SCLK cycle time
SCLK low time
SCLK high time
LATCH delay time
LATCH high time
Data setup time
Data hold time
LATCH low time
CLEAR pulse width
CLEAR activation time
SCLK cycle time
SCLK low time
SCLK high time
LATCH delay time
LATCH high time
Data setup time
Data hold time
LATCH low time
Serial output delay time (CL SDO = 50 pF)4
LATCH rising edge to SDO tristate
SCLK cycle time
SCLK low time
SCLK high time
LATCH delay time
LATCH high time
Data setup time
Data hold time
LATCH low time
Serial output delay time (CL SDO = 50 pF)4
1 Guaranteed by characterization but not production tested.
2 All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.
3 See Figure 2, Figure 3, and Figure 4.
4 CLSDO = capacitive load on SDO output.
Rev. H | Page 6 of 30

6 Page









AD5420 pdf, datenblatt
AD5410/AD5420
0.10
0.05
0
AVDD = 24V
–0.05
–0.10
–0.15
–0.20
–0.25
–40
4mA TO 20mA INTERNAL RSET
0mA TO 20mA INTERNAL RSET
0mA TO 24mA INTERNAL RSET
4mA TO 20mA EXTERNAL RSET
0mA TO 20mA EXTERNAL RSET
0mA TO 24mA EXTERNAL RSET
–20 0 20 40
TEMPERATURE (°C)
60
Figure 13. Total Unadjusted Error vs. Temperature
80
0.10
0.05
AVDD = 24V
0
–0.05
–0.10
–0.15
–0.20
–0.25
–40
0.06
4mA TO 20mA INTERNAL RSET
0mA TO 20mA INTERNAL RSET
0mA TO 24mA INTERNAL RSET
4mA TO 20mA EXTERNAL RSET
0mA TO 20mA EXTERNAL RSET
0mA TO 24mA EXTERNAL RSET
–20 0 20 40 60
TEMPERATURE (°C)
Figure 14. Offset Error vs. Temperature
80
0.04
0.02
AVDD = 24V
0
–0.02
–0.04
–0.06
–0.08
–0.10
–40
4mA TO 20mA INTERNAL RSET
0mA TO 20mA INTERNAL RSET
0mA TO 24mA INTERNAL RSET
4mA TO 20mA EXTERNAL RSET
0mA TO 20mA EXTERNAL RSET
0mA TO 24mA EXTERNAL RSET
–20 0 20 40 60
TEMPERATURE (°C)
Figure 15. Gain Error vs. Temperature
80
Data Sheet
0.015
0.010
TA = 25°C
0mA TO 24mA RANGE
0.005
0
–0.005
–0.010
–0.015
10 15 20 25 30 35 40
AVDD (V)
Figure 16. Integral Nonlinearity Error vs. AVDD, External RSET
0.020
0.015
0.010
TA = 25°C
0mA TO 24mA RANGE
0.005
0
–0.005
–0.010
–0.015
–0.020
10 15 20 25 30 35 40
AVDD (V)
Figure 17. Integral Nonlinearity Error vs. AVDD, Internal RSET
1.0
0.8 TA = 25°C
0mA TO 24mA RANGE
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
10 15 20 25 30 35 40
AVDD (V)
Figure 18. Differential Nonlinearity Error vs. AVDD, External RSET
Rev. H | Page 12 of 30

12 Page





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