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AD5721 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD5721
Beschreibung Voltage Output DAC
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD5721 Datasheet, Funktion
Data Sheet
Multiple Range, 16-/12-Bit,
Bipolar/Unipolar, Voltage Output DACs
AD5761/AD5721
FEATURES
8 software-programmable output ranges: 0 V to 5 V, 0 V to 10 V,
0 V to 16 V, 0 V to 20 V, ±3 V, ±5 V, ±10 V, −2.5 V to +7.5 V;
5% overrange
Total unadjusted error (TUE): 0.1% FSR maximum
16-bit resolution: ±2 LSB maximum INL
Guaranteed monotonicity: ±1 LSB maximum
Single channel, 16-/12-bit DACs
Settling time: 7.5 µs typical
Integrated reference buffers
Low noise: 35 nV/√Hz
Low glitch: 1 nV-sec
1.8 V logic compatibility
Asynchronous updating via LDAC
Asynchronous RESET to zero scale/midscale
DSP/microcontroller-compatible serial interface
Robust 4 kV HBM ESD rating
Available in 16-lead TSSOP and 16-lead LFCSP
Operating temperature range: −40°C to +125°C
APPLICATIONS
Industrial automation
Instrumentation, data acquisition
Open-/closed-loop servo control, process control
Programmable logic controllers
GENERAL DESCRIPTION
The AD5761/AD5721 are single channel, 16-/12-bit serial input,
voltage output, digital-to-analog converters (DACs). They operate
from single supply voltages from 4.75 V to 30 V or dual supply
voltages from −16.5 V to 0 V VSS and 4.75 V to 16.5 V VDD. The
integrated output amplifier and reference buffer provide a very
easy to use, universal solution.
The devices offer guaranteed monotonicity, integral nonlinearity
(INL) of ±2 LSB maximum, 35 nV/√Hz noise, and 7.5 µs settling
time on selected ranges.
The AD5761/AD5721 use a serial interface that operates at
clock rates of up to 50 MHz and are compatible with DSP and
microcontroller interface standards. Double buffering allows
the asynchronous updating of the DAC output. The input
coding is user-selectable twos complement or straight binary.
The asynchronous reset function resets all registers to their
default state. The output range is user selectable, via the
RA[2:0] bits in the control register.
The devices available in the 16-lead TSSOP and in the 16-lead
LFCSP offer guaranteed specifications over the −40°C to +125°C
industrial temperature range.
Table 1. Pin-Compatible Devices
Device
Description
AD5761R/AD5721R AD5761/AD5721 with internal reference
FUNCTIONAL BLOCK DIAGRAM
VDD
VREFIN
DVCC
ALERT
SDI
SCLK
SYNC
SDO
RESET
CLEAR
AD5761/AD5721
INPUT SHIFT
REGISTER
AND
CONTROL
LOGIC
12/16
INPUT
REG
REFERENCE
BUFFERS
DAC 12/16 12-BIT/
REG
16-BIT
DAC
DNC
DGND VSS
LDAC
AGND
NOTES
1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.
Figure 1.
VOUT
0V TO 5V
0V TO 10V
0V TO 16V
0V TO 20V
±3V
±5V
±10V
−2.5V TO +7.5V
Rev. B
Document Feedback
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2015–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com






AD5721 Datasheet, Funktion
AD5761/AD5721
Data Sheet
TIMING CHARACTERISTICS
DVCC = 1.7 V to 5.5 V, all specifications TMIN to TMAX, unless otherwise noted.
Table 4.
Parameter
t11
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
Limit at TMIN to TMAX
20
10
10
15
10
20
5
5
10
20
20
9
7.5
20
200
10
40
t17 50
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
µs typ
µs typ
ns min
ns typ
ns min
ns max
ns min
Description
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
SCLK falling edge to SYNC rising edge time
Minimum SYNC high time (write mode)
Data setup time
Data hold time
LDAC falling edge to SYNC falling edge
SYNC rising edge to LDAC falling edge
LDAC pulse width low
DAC output settling time, 20 V step to 1 LSB at 16-bit resolution (see Table 3)
DAC output settling time, 10 V step to 1 LSB at 16-bit resolution
CLEAR pulse width low
CLEAR pulse activation time
SYNC rising edge to SCLK falling edge
SCLK rising edge to SDO valid (CL_SDO = 15 pF, where CL_SDO is the capacitive load on the SDO
output)
Minimum SYNC high time (readback/daisy-chain mode)
1 Maximum SCLK frequency is 50 MHz for write mode and 33 MHz for readback mode.
Timing Diagrams
SCLK
SYNC
SDI
LDAC
VOUT
VOUT
1
t6
t4
2
t7
DB23
t9
t1
24
t3 t2
t5
t8
DB0
t10
t11
t12
t12
CLEAR
t13
VOUT
t14
Figure 2. Serial Interface Timing Diagram
Rev. B | Page 6 of 31

6 Page









AD5721 pdf, datenblatt
AD5761/AD5721
3
MAXIMUM INL, 0V TO 5V SPAN
MAXIMUM INL, ±10V SPAN
MINIMUM INL, 0V TO 5V SPAN
2 MINIMUM INL, ±10V SPAN
1
0
VDD = +21V
VSS = –11V
–1
–2
–3
2.00
2.25
2.50
2.75
REFERENCE VOLTAGE (V)
Figure 19. INL Error vs. Reference Voltage
3.00
1.0
MAXIMUM DNL, 0V TO 5V SPAN
0.8
MAXIMUM DNL, ±10V SPAN
MINIMUM DNL, 0V TO 5V SPAN
MINIMUM DNL, ±10V SPAN
0.6
VDD = +21V
VSS = –11V
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
2.00
2.25 2.50 2.75
REFERENCE VOLTAGE (V)
3.00
Figure 20. DNL Error vs. Reference Voltage
0.010
0.008
0V TO 5V SPAN
0V TO 10V SPAN
VDD = +21V
VSS = –11V
0.006
0.004
0.002
0
–0.002
–0.004
–0.006
–0.008
–0.010
–40
–20 0
25 50 85 105
TEMPERATURE (°C)
Figure 21. Zero-Scale Error vs. Temperature
125
Data Sheet
0.006
0.004
VDD = +21V
VSS = –11V
0V TO 5V SPAN
±10V SPAN
0.002
0
–0.002
–0.004
–0.006
–40
–20 0
25 50 85 105
TEMPERATURE (°C)
Figure 22. Midscale Error vs. Temperature
125
0.006
0.004
VDD = +21V
VSS = –11V
0V TO 5V SPAN
±10V SPAN
0.002
0
–0.002
–0.004
–0.006
–40
–20 0
25 50 85 105
TEMPERATURE (°C)
Figure 23. Full-Scale Error vs. Temperature
125
0.10
VDD = +21V
0.08 VSS = –11V
0V TO 5V SPAN
±10V SPAN
0.06
0.04
0.02
0
–0.02
–0.04
–0.06
–0.08
–0.10
–40
–20 0
25 50 85 105
TEMPERATURE (°C)
Figure 24. Gain Error vs. Temperature
125
Rev. B | Page 12 of 31

12 Page





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