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IDT70V9199 Schematic ( PDF Datasheet ) - IDT

Teilenummer IDT70V9199
Beschreibung HIGH-SPEED 3.3V 128K x9/x8 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM
Hersteller IDT
Logo IDT Logo 




Gesamt 17 Seiten
IDT70V9199 Datasheet, Funktion
HIGH-SPEED 3.3V
128K x9/x8
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
IDT70V9199/099L
Features:
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
– Commercial: 6/7.5/9/12ns (max.)
– Industrial: 9ns (max.)
Low-power operation
– IDT70V9199/099L
Active: 500mW (typ.)
Standby: 1.5mW (typ.)
Flow-Through or Pipelined output mode on either port via
the FT/PIPE pins
Dual chip enables allow for depth expansion without
additional logic
Counter enable and reset features
Full synchronous operation on both ports
– 3.5ns setup to clock and 0ns hold on all control, data, and
address inputs
– Data input, address, and control registers
– Fast 6.5ns clock to data out in the Pipelined output mode
– Self-timed write allows fast cycle time
– 10ns cycle time, 100MHz operation in Pipelined output mode
LVTTL- compatible, single 3.3V (±0.3V) power supply
Industrial temperature range (–40°C to +85°C) is
available for selected speeds
Available in a 100-pin Thin Quad Flatpack (TQFP)
Functional Block Diagram
R/WL
OEL
CE0L
CE1L
1
0
0/1
R/WR
OER
CE0R
1 CE1R
0
0/1
FT/PIPEL
I/O0L - I/O8L(1)
0/1 1
0
I/O
Control
I/O
Control
0 1 0/1
FT/PIPER
I/O0R - I/O8R(1.)
A16L
A0L
CLKL
ADSL
CNTENL
CNTRSTL
NOTE:
1. I/O0X - I/O7X for IDT70V9099.
Counter/
Address
Reg.
©2003 Integrated Device Technology, Inc.
MEMORY
ARRAY
1
Counter/
Address
Reg.
A16R
A0R
CLKR
ADSR
CNTENR
CNTRSTR
4859 drw 01
APRIL 2003
DSC-4859/3






IDT70V9199 Datasheet, Funktion
IDT70V9199/099L
High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature Supply Voltage Range(3) (VDD = 3.3V ± 0.3V)
70V9199/099L6
Com'l Only
70V9199/099L7
Com'l Only
70V9199/099L9
Com'l & Ind
70V9199/099L12
Com'l Only
Symbol
Parameter
Test Condition
Version Typ.(4) Max. Typ.(4) Max. Typ.(4) Max. Typ.(4) Max. Unit
IDD Dynamic Operating CEL and CER= VIL,
Current (Both
Outputs Disabled,
Ports Active)
f = fMAX(1)
COM'L L 220 280 200 250 175 230 150 200 mA
IND L ____ ____ ____ ____ 180 240 ____ ____
ISB1 Standby Current
(Both Ports - TTL
Level Inputs)
CEL = CER = VIH
f = fMAX(1)
COM'L L 60 85 50 75 40 65 30 50 mA
IND L ____ ____ ____ ____ 50 70 ____ ____
ISB2 Standby
Current (One
Port - TTL
Level Inputs)
CE"A" = VIL and
COM'L L 145 185 130 165 110 145 95 130 mA
CE"B" = VIH(5)
Active Port Outputs Disabled, IND
f=fMAX(1)
L ____
____
____
____
110 155 ____
____
ISB3 Full Standby
Current (Both
Ports - CMOS
Level Inputs)
Both Ports CEL and
CER > VDD - 0.2V,
VIN > VDD - 0.2V or
VIN < 0.2V, f = 0(2)
COM'L L 0.4 2 0.4 2 0.4 2 0.4 2 mA
IND L ____ ____ ____ ____ 0.4 2 ____ ____
ISB4 Full Standby
Current (One
Port - CMOS
Level Inputs)
CE"A" < 0.2V and
COM'L L 145 180 130 160 100 140 90 125 mA
CE"B" > VDD - 0.2V(5)
VIN > VDD - 0.2V or
IND L
VIN < 0.2V, Active Port,
100 155____ ____ ____ ____
____ ____
Outputs Disabled, f = fMAX(1)
NOTES:
4859 tbl 09
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input
levels of GND to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. VDD = 3.3V, TA = 25°C for Typ, and are not production tested. IDD DC(f=0) = 90mA (Typ).
5. CEX = VIL means CE0X = VIL and CE1X = VIH
CEX = VIH means CE0X = VIH or CE1X = VIL
CEX < 0.2V means CE0X < 0.2V and CE1X > VDD - 0.2V
CEX > VDD - 0.2V means CE0X > VDD - 0.2V or CE1X < 0.2V
"X" represents "L" for left port or "R" for right port.
6.462

6 Page









IDT70V9199 pdf, datenblatt
IDT70V9199/099L
High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE = VIL)(3)
tCYC1
tCH1
tCL1
CLK
CE0
CE1
R/W
tSC tHC
tSW tHW
tSW tHW
ADDRESS(4)
An
tSA tHA
An +1
DATAIN
DATAOUT
(2)
tCD1
tCD1
Qn
READ
tDC
An + 2
An + 2
An + 3
An + 4
tSD tHD
Dn + 2
tCD1
tCD1
Qn + 1
tCKHZ (1)
NOP (5)
WRITE
Qn + 3
tCKLZ(1)
tDC
READ
4859 drw 12
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE Controlled)(3)
tCYC1
tCH1
tCL1
CLK
CE0
CE1
R/W
tSC tHC
tSW tHW
tSW tHW
ADDRESS(4)
DATAIN
DATAOUT
An
tSA tHA
tCD1
(2)
An +1
An + 2
tSD tHD
Dn + 2
tDC
Qn
tOHZ (1)
An + 3
Dn + 3
An + 4
An + 5
tOE
tCD1
(1)
tCKLZ
tCD1
Qn + 4
tDC
OE
READ
WRITE
READ
4859 drw 13
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
3. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. "NOP" is "No Operation".
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for
reference use only.
5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
6.1422

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