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PDF IDT70V7339S Data sheet ( Hoja de datos )
| Número de pieza | IDT70V7339S | |
| Descripción | HIGH-SPEED 3.3V 512K x 18 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM | |
| Fabricantes | IDT | |
| Logotipo |  |
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HIGH-SPEED 3.3V 512K x 18
SYNCHRONOUS
BANK-SWITCHABLE
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
IDT70V7339S
Features:
◆ 512K x 18 Synchronous Bank-Switchable Dual-ported SRAM
Architecture
– 64 independent 8K x 18 banks
– 9 megabits of memory on chip
◆ Bank access controlled via bank address pins
◆ High-speed data access
– Commercial: 3.4ns (200MHz)/3.6ns (166MHz)/
4.2ns (133MHz) (max.)
– Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)
◆ Selectable Pipelined or Flow-Through output mode
◆ Counter enable and repeat features
◆ Dual chip enables allow for depth expansion without
additional logic
◆ Full synchronous operation on both ports
– 5ns cycle time, 200MHz operation (14Gbps bandwidth)
– Fast 3.4ns clock to data out
– 1.5ns setup to clock and 0.5ns hold on all control, data, and
address inputs @ 200MHz
– Data input, address, byte enable and control registers
– Self-timed write allows fast cycle time
◆ Separate byte controls for multiplexed bus and bus match-
ing compatibility
◆ LVTTL- compatible, 3.3V (±150mV) power supply
for core
◆ LVTTL compatible, selectable 3.3V (±150mV) or 2.5V
(±100mV) power supply for I/Os and control signals on each
port
◆ Industrial temperature range (-40°C to +85°C) is
available at 166MHz and 133MHz
◆ Available in 208-pin fine pitch Ball Grid Array (fpBGA) and
256-pin Ball Grid Array (BGA)
◆ Supports JTAG features compliant with IEEE 1149.1
◆ Green parts available, see ordering information
Functional Block Diagram
PL/FTL
OPTL
CLKL
ADSL
CNTENL
REPEATL
R/WL
CE0L
CE1L
UBL
LBL
OEL
CONTROL
LOGIC
I/O0L-17L
I/O
CONTROL
A12L
A0L
BA5L
BA4L
BA3L
BA2L
BA1L
BA0L
ADDRESS
DECODE
BANK
DECODE
NOTE:
1. TheBank-Switchabledual-portusesatrueSRAMcore
instead of the traditional dual-port SRAM core. As a result, it
has unique operating characteristics. Please refer to the
functionaldescriptiononpage18fordetails.
MUX
8Kx18
MEMORY
ARRAY
(BANK 0)
MUX
MUX
8Kx18
MEMORY
ARRAY
(BANK 1)
MUX
MUX
8Kx18
MEMORY
ARRAY
(BANK 63)
MUX
TDI
TDO
JTAG
TMS
TCK
TRST
©2015 Integrated Device Technology, Inc.
1
CONTROL
LOGIC
PL/FTR
OPTR
CLKR
ADSR
CNTENR
REPEATR
R/WR
CE0R
CE1R
UBR
LBR
OER
I/O
CONTROL
I/O0R-17R
ADDRESS
DECODE
BANK
DECODE
A12R
A0R
BA5R
BA4R
BA3R
BA2R
BA1R
BA0R
5628 drw 01
,
AUGUST 2015
DSC 5628/10
1 page  
IDT70V7339S
High-Speed 512K x 18 Synchronous Bank-Switchable Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table I—Read/Write and Enable Control(1,2,3,4)
OE3 CLK CE0 CE1 UB
Upper Byte Lower Byte
LB R/W
I/O9-17
I/O0-8
MODE
X ↑ HX X X X
High-Z
High-Z Deselected–Power Down
X↑X LXXX
High-Z
High-Z Deselected–Power Down
X↑ L HHHX
High-Z
High-Z All Bytes Deselected
X↑LHHL L
High-Z
DIN Write to Lower Byte Only
X ↑ L H L H L DIN High-Z Write to Upper Byte Only
X↑LHLL L
DIN
DIN Write to both Bytes
L ↑ L HHL H
High-Z
DOUT Read Lower Byte Only
L↑L HL HH
DOUT
High-Z Read Upper Byte Only
L↑L HL L H
DOUT
DOUT Read both Bytes
HX X X X X X
High-Z
High-Z Outputs Disabled
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. ADS,CNTEN,REPEAT aresetasappropriateforaddressaccess.RefertoTruthTableIIfordetails.
3. OEisanasynchronousinputsignal.
4. Itispossibletoreadorwriteanycombinationofbytesduringagivenaccess.Afewrepresentativesampleshavebeenillustratedhere.
5628 tbl 02
Truth Table II—Address and Address Counter Control(1,2,7)
Previous Addr
Address Address Used CLK ADS CNTEN REPEAT(6)
I/O(3)
MODE
An
X An ↑ L(4) X
H DI/O (n) External Address Used
X
An An + 1 ↑ H L(5)
H DI/O(n+1) Counter Enabled—Internal Address generation
X An + 1 An + 1 ↑ H H
H DI/O(n+1) External Addre ss Blocked—Counter disab led (An + 1 reused)
X X An ↑ X X L(4) DI/O(0) Counter Set to last valid ADS load
NOTES:
5628 tbl 03
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. ReadandwriteoperationsarecontrolledbytheappropriatesettingofR/W,CE0,CE1,UB/LB andOE.
3. Outputsconfiguredinflow-throughoutputmode:ifoutputsareinpipelinedmodethedataoutwillbedelayedbyonecycle.
4. ADS and REPEAT areindependentofallothermemorycontrolsignalsincludingCE0,CE1 and UB/LB
5. Theaddresscounteradvancesif CNTEN =VILontherisingedgeofCLK,regardlessofallothermemorycontrolsignalsincludingCE0,CE1,UB/LB.
6. WhenREPEATisasserted,thecounterwillresettothelastvalidaddressloadedviaADS.Thisvalueisnotsetatpower-up:aknownlocationshouldbeloadedviaADSduringinitialization
if desired. Any subsequent ADS access during operations will update the REPEAT address location.
7. Thecounterincludesbankaddressandinternaladdress.Thecounterwilladvanceacrossbankboundaries.Forexample,ifthecounterisinBank0,ataddressFFFh,andisadvancedone
location, it will move to address 0h in Bank 1. By the same token, the counter at FFFh in Bank 63 will advance to 0h in Bank 0. Refer to Timing Waveform of Counter Repeat, page 17. Care
shouldbetakenduringoperationtoavoidhavingbothcounterspointtothesamebank(i.e.,ensureBA0L -BA5L ≠ BA0R-BA5R),asthisconditionwillinvalidatetheaccessforbothports.
Please refer to the functional description on page 18 for details.
6.452
5 Page 
IDT70V7339S
High-Speed 512K x 18 Synchronous Bank-Switchable Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle for Pipelined Operation
(ADS Operation) (FT/PIPE'X' = VIH)(2)
tCH2
tCYC2
tCL2
CLK
CE0
CE1
UB/LB
tSC tHC
tSB tHB
tSB tHB
(5)
tSC tHC
(3)
R/W
ADDRESS(4)
tSW tHW
tSA tHA
An
DATAOUT
tCKLZ (1)
(1 Latency)
(1)
OE
An + 1
tCD2
An + 2
tDC
Qn
An + 3
Qn + 1
tOHZ
tOLZ
Qn + 2 (5)
tOE
5628 drw 06
Timing Waveform of Read Cycle for Flow-through Output
(FT/PIPE"X" = VIL)(2,6)
tCYC1
tCH1
tCL1
CLK
CE0
CE1
BEn
R/W
ADDRESS(4)
DATAOUT
tSC tHC
tSB tHB
tSW tHW
tSA tHA
An
tCD1
tCKLZ
An + 1
tDC
Qn
tSC tHC
(3)
tSB tHB
(5)
An + 2
Qn + 1
tOHZ
An + 3
tCKHZ
Qn + 2 (5)
tOLZ
tDC
OE (1)
NOTES:
tOE
1. OEisasynchronouslycontrolled;allotherinputsaresynchronoustotherisingclockedge.
2. ADS = VIL, CNTEN and REPEAT = VIH.
3. Theoutputisdisabled(High-Impedancestate)by CE0=VIH,CE1=VIL,UB/LB=VIH followingthenextrisingedgeoftheclock.Referto
Truth Table 1.
4. Addressesdonothavetobeaccessedsequentiallysince ADS=VILconstantlyloadstheaddressontherisingedgeoftheCLK;numbers
are for reference use only.
5. IfUB/LBwas HIGH,thentheappropriateByteofDATAOUT forQn+2wouldbedisabled(High-Impedancestate).
6. "x"denotesLeftorRightport.Thediagramiswithrespecttothatport.
5628 drw 07
6.1412
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