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IDT70V3599S Schematic ( PDF Datasheet ) - Integrated Device Technology

Teilenummer IDT70V3599S
Beschreibung HIGH-SPEED 3.3V 128/64K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM
Hersteller Integrated Device Technology
Logo Integrated Device Technology Logo 




Gesamt 23 Seiten
IDT70V3599S Datasheet, Funktion
HIGH-SPEED 3.3V
128/64K x 36
SYNCHRONOUS
DUAL-PORT STATIC RAM
IDT70V3599/89S
WITH 3.3V OR 2.5V INTERFACE
Features:
True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed data access
– Commercial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)
– Industrial: 4.2ns (133MHz) (max.)
Selectable Pipelined or Flow-Through output mode
Counter enable and repeat features
Dual chip enables allow for depth expansion without
additional logic
Full synchronous operation on both ports
– 6ns cycle time, 166MHz operation (12Gbps bandwidth)
– Fast 3.6ns clock to data out
– 1.7ns setup to clock and 0.5ns hold on all control, data, and
address inputs @ 166MHz
– Data input, address, byte enable and control registers
– Self-timed write allows fast cycle time
Separate byte controls for multiplexed bus and bus
matching compatibility
Dual Cycle Deselect (DCD) for Pipelined Output mode
LVTTL- compatible, 3.3V (±150mV) power supply
for core
LVTTL compatible, selectable 3.3V (±150mV) or 2.5V
(±100mV) power supply for I/Os and control signals on
each port
Industrial temperature range (-40°C to +85°C) is
available at 133MHz.
Available in a 208-pin Plastic Quad Flatpack (PQFP),
208-pin fine pitch Ball Grid Array (fpBGA), and 256-pin Ball
Grid Array (BGA)
Supports JTAG features compliant with IEEE 1149.1
Functional Block Diagram
BE3L
BE2L
BE1L
BE0L
BE3R
BE2R
BE1R
BE0R
FT/PIPEL
R/WL
CE0L
CE1L
OEL
0a 1a
1/0
a
0b 1b
b
0c 1c
c
0d 1d
d
1
0
1/0
BB BBBB BB
WW WWWW WW
01 2332 10
L L L L RR RR
Dout0-8_L
Dout9-17_L
Dout18-26_L
Dout27-35_L
Dout0-8_R
Dout9-17_R
Dout18-26_R
Dout27-35_R
FT/PIPEL
1d 0d 1c 0c 1b 0b 1a 0a
0/1
a b cd
I/O0L - I/O35 L
CLKL
A16L(1)
A0L
REPEATL
ADSL
CNTENL
NOTE:
1. A16 is a NC for IDT70V3589.
©2003 Integrated Device Technology, Inc.
Counter/
Address
Reg.
TDI
TDO
128K x 36
MEMORY
ARRAY
Din_L
Din_R
ADDR_L
ADDR_R
JTAG
1
1d 0d
d
1c 0c
c
1b 0b
b
1a 0a
1/0
a
1
0
1 /0
FT/PIPER
R/WR
CE0R
CE1R
OER
0a 1a 0b 1b 0c 1c 0d 1d
d cba
0/1
FT/PIPER
Counter/
Address
Reg.
TCK
TMS
TRST
I/O0R - I/O35R
CLKR
A 16 R( 1)
A0R
REPEATR
ADSR
CNTENR
,
5617 tbl 01
MAY 2003
DSC 5617/6






IDT70V3599S Datasheet, Funktion
IDT70V3599/89S
High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Truth Table I—Read/Write and Enable Control(1,2,3,4)
Byte 3
OE CLK CE0 CE1 BE3 BE2 BE1 BE0 R/W I/O27-35
Byte 2
I/O18-26
Byte 1
I/O9-17
Byte 0
I/O0-8
MODE
X H X X X X X X High-Z High-Z High-Z High-Z Deselected–Power Down
X X L X X X X X High-Z High-Z High-Z High-Z Deselected–Power Down
X L H H H H H X High-Z High-Z High-Z High-Z All Bytes Deselected
X L H H H H L L High-Z High-Z High-Z
DIN Write to Byte 0 Only
X L H H H L H L High-Z High-Z DIN High-Z Write to Byte 1 Only
X L H H L H H L High-Z DIN High-Z High-Z Write to Byte 2 Only
X L H L H H H L DIN High-Z High-Z High-Z Write to Byte 3 Only
X L H H H L L L High-Z High-Z
DIN
DIN Write to Lower 2 Bytes Only
XL HL L HHL
DIN
DIN High-Z High-Z Write to Upper 2 bytes Only
XL HL L L L L
DIN
DIN
DIN
DIN Write to All Bytes
L L H H H H L H High-Z High-Z High-Z DOUT Read Byte 0 Only
L L H H H L H H High-Z High-Z DOUT High-Z Read Byte 1 Only
L L H H L H H H High-Z DOUT High-Z High-Z Read Byte 2 Only
L L H L H H H H DOUT High-Z High-Z High-Z Read Byte 3 Only
L L H H H L L H High-Z High-Z DOUT
DOUT Read Lower 2 Bytes Only
L L H L L H H H DOUT
DOUT High-Z High-Z Read Upper 2 Bytes Only
L L H L L L L H DOUT
DOUT
DOUT
DOUT Read All Bytes
H L H L L L L X High-Z High-Z High-Z High-Z Outputs Disabled
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. ADS, CNTEN, REPEAT = VIH.
3. OE is an asynchronous input signal.
4. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here.
5617 tbl 02
Truth Table II—Address Counter Control(1,2)
Previous Internal
External Internal Address
Address Address
Used
CLK ADS CNTEN REPEAT(6)
I/O(3)
MODE
X
X
An
X
X
L(4) DI/O(0) Counter Reset to last valid ADS load
An
X
An L(4) X
H DI/O (n) External Address Used
An Ap Ap H H H DI/O(p) External Address Blocked—Counter disabled (Ap reused)
X
Ap
Ap + 1
H
L(5)
H DI/O(p+1) Counter Enabled—Internal Address generation
NOTES:
5617 tbl 03
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. Read and write operations are controlled by the appropriate setting of R/W, CE0, CE1, BEn and OE.
3. Outputs configured in flow-through output mode: if outputs are in pipelined mode the date out will be delayed by one cycle.
4. ADS and REPEAT are independent of all other memory control signals including CE0, CE1 and BEn
5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other memory control signals including CE0, CE1, BEn.
6. When REPEAT is asserted, the counter will reset to the last valid address loaded via ADS. This value is not set at power-up: a known location should be loaded
via ADS during initialization if desired. Any subsequent ADS access during operations will update the REPEAT address location.
66.42

6 Page









IDT70V3599S pdf, datenblatt
IDT70V3599/89S
High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle for Pipelined Operation
(FT/PIPE'X' = VIH)(2)
tCH2
tCYC2
tCL2
CLK
CE0
CE1
BEn
tSC tHC
tSB tHB
tSB tHB
(5)
tSC tHC
(3)
R/W
ADDRESS(4)
DATAOUT
(1)
OE
tSW tHW
tSA tHA
An
An + 1
(1 Latency)
tCD2
tCKLZ (1)
An + 2
tDC
Qn
An + 3
Qn + 1
tOHZ
tOLZ
Qn + 2 (5)
tOE
5617 drw 06
Timing Waveform of Read Cycle for Flow-through Output
(FT/PIPE"X" = VIL)(2,6)
tCYC1
tCH1
tCL1
CLK
CE0
CE1
BEn
tSC tHC
tSB tHB
tSC tHC
(3)
tSB tHB
R/W
ADDRESS(4)
DATAOUT
tSW tHW
tSA tHA
An
tCD1
tCKLZ
An + 1
tDC
Qn
An + 2
Qn + 1
tOHZ
An + 3
tCKHZ
Qn + 2 (5)
tOLZ
tDC
OE (1)
NOTES:
tOE
5617 drw 07
1. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
2. ADS = VIL, CNTEN and REPEAT = VIH.
3. The output is disabled (High-Impedance state) by CE0 = VIH, CE1 = VIL, BEn = VIH following the next rising edge of the clock. Refer to
Truth Table 1.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
5. If BEn was HIGH, then the appropriate Byte of DATAOUT for Qn + 2 would be disabled (High-Impedance state).
6. "x" denotes Left or Right port. The diagram is with respect to that port.
61.422

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