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IDT709169 Schematic ( PDF Datasheet ) - IDT

Teilenummer IDT709169
Beschreibung HIGH-SPEED 16/8K x 9 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM
Hersteller IDT
Logo IDT Logo 




Gesamt 16 Seiten
IDT709169 Datasheet, Funktion
HIGH-SPEED 16/8K x 9
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
IDT709169/59L
Features
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
– Commercial: 6.5/7.5/9ns (max.)
Industrial: 7.5ns (max.)
Low-power operation
– IDT709169/59L
Active: 925mW (typ.)
Standby: 2.5mW (typ.)
Flow-Through or Pipelined output mode on either Port via
the FT/PIPE pins
Counter enable and reset features
Dual chip enables allow for depth expansion without
additional logic
Functional Block Diagram
Full synchronous operation on both ports
– 3.5ns setup to clock and 0ns hold on all control, data, and
address inputs
– Data input, address, and control registers
– Fast 6.5ns clock to data out in the Pipelined output mode
– Self-timed write allows fast cycle time
– 10ns cycle time,100MHz operation in Pipelined output mode
TTL- compatible, single 5V (±10%) power supply
Industrial temperature range (–40°C to +85°C) is
available for 83MHz
Available in a 100-pin Thin Quad Flatpack (TQFP) and 100-
pin fine pitch Ball Grid Array (fpBGA) packages.
R/WL
OEL
CE0L
CE1L
1
0
0/1
R/WR
OER
CE0R
1 CE1R
0
0/1
FT/PIPEL
I/O0L - I/O8L
0/1 1
0
I/O
Control
I/O
Control
0 1 0/1
A13L(1)
A0L
CLKL
ADSL
CNTENL
CNTRSTL
Counter/
Address
Reg.
MEMORY
ARRAY
Counter/
Address
Reg.
NOTE:
1. A13 is a NC for IDT709159.
FT/PIPER
I/O0R - I/O8R
A13R(1)
A0R
CLKR
ADSR
CNTENR
CNTRSTR
5653 drw 01
©2009 Integrated Device Technology, Inc.
1
JANUARY 2009
DSC-5653/3






IDT709169 Datasheet, Funktion
IDT709169/59L
High-Speed 16/8K x 9 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature Supply Voltage Range (VCC = 5.0V ± 10%)
709169/59L
Symbol
|ILI|
|ILO|
VOL
Parameter
Input Leakage Current(1)
Output Leakage Current
Output Low Voltage
Test Conditions
VCC = 5.5V, VIN = 0V to VCC
CE0 = VIH or CE1 = VIL, VOUT = 0V to VCC
IOL = +4mA
Min. Max. Unit
___ 5 µ A
___ 5 µ A
___ 0.4 V
VOH Output High Voltage
NOTE:
1. At Vcc < 2.0V input leakages are undefined.
IOH = -4mA
2.4 ___ V
5653 tbl 08
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(3) (VCC = 5V ± 10%)
709169/59L6
Com'l Only
709169/59L7
Com'l & Ind
709169/59L9
Com'l Only
Symbol
Parameter
Test Condition
Version
Typ.(4) Max. Typ.(4) Max. Typ.(4) Max. Unit
ICC Dynamic Operating
Current
(Both Ports Active)
CEL and CER= VIL
Outputs Disabled
f = fMAX(1)
COM'L L 230 430 210 400 185 360 mA
IND
L ____
____ 210 440 ____ ____
ISB1 Standby Current
(Both Ports - TTL
Level Inputs)
CEL = CER = VIH
f = fMAX(1)
COM'L L 45 115 40 105 35 95 mA
IND L ____ ____ 40 120 ____ ____
ISB2 Standby Current
(One Port - TTL
Level Inputs)
CE"A" = VIL and
CE"B" = VIH(3)
Active Port Outputs
Disabled, f=fMAX(1)
COM'L L 150 235 135 220 120 205 mA
IND L ____ _____ 135 235 ____ ____
ISB3 Full Standby Current
(Both Ports -
CMOS Level Inputs)
Both Ports CER and
CEL > VCC - 0.2V
VIN > VCC - 0.2V or
VIN < 0.2V, f = 0(2)
COM'L L 0.5 3.0 0.5 3.0 0.5 3.0 mA
IND L ____ _____ 0.5 3.0 ____ ____
ISB4 Full Standby Current
CE"A" < 0.2V and
COM'L L 160 210 130 190 110 170 mA
(One Port -
CE"B" > VCC - 0.2V(5)
CMOS Level Inputs)
VIN > VCC - 0.2V or
IND L
VIN < 0.2V, Active Port
____ _____ 130 205 ____ ____
Outputs Disabled , f = fMAX(1)
5653 tbl 09
NOTES:
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input levels of
GND to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. Vcc = 5V, TA = 25°C for Typ, and are not production tested. ICC DC(f=0) = 150mA (Typ).
5. CEX = VIL means CE0X = VIL and CE1X = VIH
CEX = VIH means CE0X = VIH or CE1X = VIL
CEX < 0.2V means CE0X < 0.2V and CE1X > VCC - 0.2V
CEX > VCC - 0.2V means CE0X > VCC - 0.2V or CE1X < 0.2V
"X" represents "L" for left port or "R" for right port.
6.642

6 Page









IDT709169 pdf, datenblatt
IDT709169/59L
High-Speed 16/8K x 9 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE = VIL)(3)
tCYC1
tCH1
tCL1
CLK
CE0
CE1
R/W
tSC tHC
tSW tHW
tSW tHW
(4)
ADDRESS
An
tSA tHA
An +1
DATAIN
DATAOUT
(2)
tCD1
tCD1
Qn
tDC
READ
An + 2
An + 2
An + 3
An + 4
tSD tHD
Dn + 2
Qn + 1
tCKHZ (1)
NOP(5)
WRITE
tCD1
tCD1
Qn + 3
tCKLZ(1)
tDC
READ
5653 drw 13
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE Controlled)(3)
tCYC1
tCH1 tCL1
CLK
CE0
CE1
R/W
tSC tHC
tSW tHW
tSW tHW
ADDRESS(4)
DATAIN
DATAOUT
OE
An
tSA tHA
tCD1
(2)
An +1
An + 2
tSD tHD
Dn + 2
tDC
Qn
tOHZ (1)
READ
An + 3
Dn + 3
WRITE
An + 4
An + 5
tOE
tCD1
(1)
tCKLZ
tCD1
Qn + 4
tDC
READ
5653 drw 14
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. Output state (High, Low, or High-impedance is determined by the previous cycle control signals.
3. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. "NOP" is "No Operation".
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only.
5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
61.422

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