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IDT709089L Schematic ( PDF Datasheet ) - Integrated Device Technology

Teilenummer IDT709089L
Beschreibung HIGH-SPEED 64K x 8 SYNCHRONOUS DUAL-PORT STATIC RAM
Hersteller Integrated Device Technology
Logo Integrated Device Technology Logo 




Gesamt 17 Seiten
IDT709089L Datasheet, Funktion
HIGH-SPEED 64K x 8
SYNCHRONOUS
DUAL-PORT STATIC RAM
PRELIMINARY
IDT709089S/L
Features:
x True Dual-Ported memory cells which allow simultaneous
access of the same memory location
x High-speed clock to data access
– Commercial: 9/12/15ns (max.)
x Low-power operation
– IDT709089S
Active: 950mW (typ.)
Standby: 5mW (typ.)
– IDT709089L
Active: 950mW (typ.)
Standby: 1mW (typ.)
x Flow-Through or Pipelined output mode on either port via
the FT/PIPE pin
x Counter enable and reset features
x Dual chip enables allow for depth expansion without
additional logic
x Full synchronous operation on both ports
– 4ns setup to clock and 1ns hold on all control, data,
and address inputs
– Data input, address, and control registers
– Fast 9ns clock to data out in the Pipelined output mode
– Self-timed write allows fast cycle time
– 15ns cycle time, 66MHz operation in the Pipelined
output mode
x TTL- compatible, single 5V (±10%) power supply
x Industrial temperature range (–40°C to +85°C) is available
for selected speeds
x Available in 100-pin Thin Quad Flatpack (TQFP) package
Functional Block Diagram
R/WL
OEL
CE0L
CE1L
1
0
0/1
R/WR
OER
CE0R
1 CE1R
0
0/1
FT/PIPEL
I/O0L - I/O7L
A15L
A0L
CLKL
ADSL
CNTENL
CNTRSTL
0/1 1
0
I/O
Control
I/O
Control
0 1 0/1
Counter/
Address
Reg.
MEMORY
ARRAY
Counter/
Address
Reg.
FT/PIPER
I/O0R - I/O7R
A15R
A0R
CLKR
ADSR
CNTENR
CNTRSTR
3242 drw 01
©2000 Integrated Device Technology, Inc.
1
FEBRUARY 2000
DSC-3242/10






IDT709089L Datasheet, Funktion
IDT709089S/L
High-Speed 64K x 8 Synchronous Dual-Port Static RAM
AC Test Conditions
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
3ns Max.
1.5V
1.5V
Figures 1,2 and 3
3242 tbl 10
Preliminary
Industrial and Commercial Temperature Ranges
DATAOUT
347
5V
893
30pF
3242 drw 04
Figure 1. AC Output Test load.
DATAOUT
347
5V
893
5pF*
3242 drw 05
Figure 2. Output Test Load
(For tCKLZ, tCKHZ, tOLZ, and tOHZ).
*Including scope and jig.
tCD1,
tCD2
(Typical, ns)
8
7
6
5
4
3
2
1
-10 pF is the I/O capacitance
of this device, and 30pF is the
AC Test Load Capacitance
0
20 40 60 80 100 120 140 160 180 200 ,
-1 Capacitance (pF)
3242 drw 06
Figure 3. Typical Output Derating (Lumped Capacitive Load).
6.642

6 Page









IDT709089L pdf, datenblatt
IDT709089S/L
High-Speed 64K x 8 Synchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Timing Waveform Flow-Through Read-to-Write-to-Read (OE = VIL)(3)
tCYC1
tCH1
tCL1
CLK
CE0
CE1
tSC tHC
R/W
tSW tHW
tSW tHW
ADDRESS(4)
An
tSA tHA
An +1
DATAIN
DATAOUT
(2)
tCD1
tCD1
Qn
READ
tDC
An + 2
An + 2
An + 3
An + 4
tSD tHD
Dn + 2
Qn + 1
tCKHZ(1)
NOP(5)
WRITE
tCD1
tCD1
Qn + 3
tCKLZ(1)
tDC
READ
3242 drw 13
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE Controlled)(3)
tCYC1
tCH1
tCL1
CLK
CE0
tSC tHC
CE1
R/W
tSW tHW
tSW tHW
ADDRESS(4)
DATAIN
DATAOUT
An
tSA tHA
tCD1
(2)
An +1
An + 2
tSD tHD
Dn + 2
tDC
Qn
tOHZ (1)
OE
READ
An + 3
Dn + 3
WRITE
An + 4
An + 5
tOE
tCD1
(1)
tCKLZ
tCD1
Qn + 4
tDC
READ
3242 drw 14
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. Output state (High, Low, or High-impedance is determined by the previous cycle control signals.
3. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only.
5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
61.422

12 Page





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