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PDF TD025THEG1 Data sheet ( Hoja de datos )
| Número de pieza | TD025THEG1 | |
| Descripción | LTPS LCD | |
| Fabricantes | toppoly | |
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TD025THEG1
Ver.: 0.01
LTPS LCD Specification
Model Name: TD025THEG1
Customer Signature
Date
This technical specification is subjected to change without notice
The information contained herein is the exclusive property and confidential document of TPO Displays Corp., and shall
not be distributed, reproduced, or disclosed in whole or in part without prior written permission of TPO Displays Corp
Page: 1/26
1 page  
TD025THEG1
3. INPUT/OUTPUT TERMINALS
3.1 TFT LCD Panel
Recommend connector:
Compatible with JAE IL-FHJ-39S-HF-A1, HRS FH23-39S-0.3SHW(0.5),
Molex SD54809 –3957 ,
Pin Symbol I/O
Description
Remark
1
CP3
C Capacitor for power setting
2
CP4
C Capacitor for power setting
3
CP5
C Capacitor for charge pump
4
CP6
C Capacitor for charge pump
5
CP7
C Capacitor for charge pump
6
CP8
C Capacitor for charge pump
7
DUMMY
--
Dummy
8
DUMMY
--
Dummy
9
PCD
C Capacitor for pre-charge data signal high
10 VCOML C Capacitor for VCOM low
11 VCOMH C Capacitor for VCOM high
12 AGND -- Analog ground
13 DUMMY -- Dummy
14 AVDD C Regulation capacitor for analog voltage
15 CP1 C Capacitor for charge pump
16 CP2 C Capacitor for charge pump
17 PWM O Power transistor gate signal for the boost converter
18 FB
I Main boost regulator feedback input.
19 LED- -- LED power: cathode
Note 1
20 DUMMY -- Dummy
21 DUMMY -- Dummy
22 LED+ -- LED power: anode
Note 1
23 GND -- Ground
24 VCC -- Power supply for digital circuit and charge pump circuit
25 VSYNC I
Vertical sync input. Negative polarity
26 HSYNC I
Horizontal sync input. Negative polarity
27 DCLK I Clock signal, latch data onto line latches at the rising edge
28 DIN0 I Data input
29 DIN1 I Data input
The information contained herein is the exclusive property and confidential document of TPO Displays Corp., and shall
not be distributed, reproduced, or disclosed in whole or in part without prior written permission of TPO Displays Corp
Page: 5/26
5 Page 
TD025THEG1
6.2
VD
HD
DIN[7:0]
Serial RGB Dummy Mode and Serial YUV 4:2:2 Mode: Vertical
tvpw
tvdm
tvbo
Valid Data
Display Area
Active Area
tvd
Odd Filed (tv)
tvdm
tvfpo
tvdm
tvbe
1 Frame
Valid Data
Display Area
Active Area
tvd
Even Filed (tv)
tvdm
tvfpe
Non-interlace Mode
VD
HD
DIN[7:0]
tvpw
tvdm
tvbo
Valid Data
Display Area
Active Area
tvd
Odd Filed (tv)
tvdm
tvfpo
tvdm
tvbe
1 Frame
Valid Data
Display Area
Active Area
tvd
Even Filed (tv)
tvdm
tvfpe
Interlace Mode
(1) Non-Interlace Mode: NTSC/QVGA
Item
Vertical Display Active
Vertical Total Time
VSYNC Pulse Width
Vertical Back Odd Field
Porch
Even Field
Vertical Front Odd Field
Porch
Even Field
Vertical Dummy Time
Symbol
tvd
tv
tvpw
tvbo
tvbe
tvfpo
tvfpe
tvdm
MIN
-
-
1
-
-
-
-
-
TYP
240
262
1
21
21
1
1
0
MAX
-
-
-
-
-
-
-
-
Unit
Line
Line
DCLK
Line
Line
Line
Line
Line
The information contained herein is the exclusive property and confidential document of TPO Displays Corp., and shall
not be distributed, reproduced, or disclosed in whole or in part without prior written permission of TPO Displays Corp
Page: 11/26
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet TD025THEG1.PDF ] | |
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