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PDF MCM6226A Data sheet ( Hoja de datos )
| Número de pieza | MCM6226A | |
| Descripción | 128K x 8 Bit Static Random Access Memory | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MCM6226A (archivo pdf) en la parte inferior de esta página. Total 6 Páginas | ||
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MOTOROLA
• SEMICONDUCTOR
TECHNICAL DATA
128K X 8 Bit Static Random
Access Memory
The MCM6226A is a 1,048,576 bit static random access memory organized as
131,072 words of 8 bits, fabricated using high-performance silicon-gate CMOS
technology. Static design eliminates the need for external clocks or timing strobes while
CMOS circuitry reduces power consumption and provides for greater reliability.
The MCM6226A is equipped with both chip enable (ET and E2) and output enable (<3)
pins, allowing for greater system flexibility and eliminating bus contention problems.
The MCM6226A is available in 400 mil, 32 lead surface-mount SOJ packages.
• Single 5 V ± 10% Power Supply
• Fast Access Times:20, 25, 35, and 45 ns
• Equal Address and Chip Enable Access Times
• All Inputs and Outputs are TTL Compatible
Three State Outputs
• Low Power Operation: 180/160/150/140 mA Maximum, Active AC
A3----I
A4----I
A?----I
A6 - - - - I
A5----I
Al0 - - - - I
A9---I
A8----I
Al----I
BLOCK DIAGRAM
ROW
DECODER
•
•
•
MEMORY MATRIX
5l2ROWSx
2048 COLUMNS
MCM6226A
~PACKAGE
400 MILSOJ
CASE 857A
PIN ASSIGNMENT
NC VCC
AO A16
A1 E2
Vi
A3 A15
A4 A14
A5 A13
A6 A12
A7 G
A8 A11
A9 E1
A10 DO?
DOO D06
D01 D05
D02 D04
VSS D03
DOO---..-I
•••
DO? - ......-+-1
E1
E2 --'""1-~'/
W-----~
G -----...q,_~
COLUMN I/O
PIN NAMES
AD - A16 ............. Address Inputs
IN ..................... Write Enable
G ................... Output Enable
E1, E2 ................ Chip Enables
DOD - DO? ..... , Data Inputs/Outputs
NC .................. No Connection
VCC ............. + 5 V Power Supply
VSS ........................ Ground
MOTOROLA FAST SRAM DATA
MCM6226A
3-45
1 page  
WRITE CYCLE 1 (W Controlled, See Notes 1,2,3, and 4)
Symbol
6226A·20
6226A·25
6226A·35
6226A-45
Parameter
Write Cycle Time
Address Setup Time
Address Valid to End of Write
Write Pulse Width
Data Valid to End of Write
Data Hold Time
Standard Alternate Min Max Min Max Min Max Min Max Unit Notes
tAVAV
twc 20 - 25 - 35 - 45 - ns 5
tAVWL
tAS
0-
0-
0-
0-
ns
tAVWH
tAW
15 -
17 -
20 -
25 -
ns
twLWH
twP
15 -
17 -
20 -
25 -
ns
tOVWH
tow
10 -
10 -
15 -
20 -
ns
tWHOX
tOH
0-
0-
0-
0-
ns
Write Low to Data High-Z
twLQZ twz 0 9 0 10 0 15 0 20 ns 6,7,8
Write High to Output Active
tWHQX
tow
5-
5-
5-
5-
ns 6,7,8
Write Recovery Time
twHAX
twR
0-
0-
0-
0-
ns
NOTES:
1. A write occurs during the overlap of E low and Wlow.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus con-
tention conditions during read and write cycles.
3. E1 and E2 are represented by E in this data sheet. E2 is of opposite polarity to E1.
4. If G goes low coincident with or after Wgoes low, the output will remain in a high-impedance state.
5. All timings are referenced from the last valid address to the first transitioning address.
6. Transition is measured ± 500 mV from steady-state voltage with load of Figure 1B.
7. This parameter is sampled and not 100% tested.
8. At any given voltage and temperature, twLQZ max is less than twHQX min both for a given device and from device to device.
Il
WRITE CYCLE 1 (W Controlled See Notes 1,2,3, and 4)
~----------- 'AVAV ----------~
A (ADDRESS)
E(CHIP ENABLE)
~-------------- 'AVWH ------------~~--~-WHAA
Vi (WRITE ENABLE)
tWLWH
tWLEH
----+-~---- 'DVWH - - -.....
D(DATAIN)
DATA VALID
~ ~",a?
I · ·~ax
--~<XXXZ)Q(DATAOUT) _ _.....;.H.;;.;;IG;;.;..H-;;..Z
.-..- - - - - H I G - H - - Z - - - - - K X X X X > -
MOTOROLA FAST SRAM DATA
MCM6226A
3-49
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet MCM6226A.PDF ] | |
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