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PDF SY58051AU Data sheet ( Hoja de datos )
| Número de pieza | SY58051AU | |
| Descripción | Ultra-Precision CML AnyGate | |
| Fabricantes | Micrel Semiconductor | |
| Logotipo |  |
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SY58051AU
Ultra-Precision CML AnyGate®
with Internal Input and Output Termination
Revision 1.0
General Description
The SY58051AU is an ultra-fast, low jitter universal logic
gate with a guaranteed maximum data or clock throughput
of 10.7Gbps or 8GHz, respectively. This AnyGate®
differential logic device will produce many logic functions
of two Boolean variables, such as AND, NAND, OR, NOR,
DELAY, or NEGATION.
The SY58051AU differential inputs include a unique
internal termination design that allows access to the
termination network throughout a VT pin. This feature
allows the device to easily interface to different logic
standards, both AC- and DC-coupled, without external
resistor-bias and termination networks. The result is a
clean, stub-free, low-jitter interface solution. The
differential CML output is optimized for environments with
internal 50Ω source termination and a 400mV output
swing.
The SY58051AU operates from a 2.5V or 3.3V supply and
is guaranteed over the full industrial temperature range of
–40°C to +85°C. The SY58051AU is part of Micrel’s
Precision Edge® product family.
Datasheets and support documentation are available on
Micrel’s web site at: www.micrel.com.
Functional Block Diagram
Precision Edge®
Features
Three matched-delay input pairs provide any logic
function: AND, NAND, OR, NOR
Guaranteed AC performance over temperature and
voltage:
DC to >10.7Gbps data rate throughput
DC to >8GHz clock fMAX
<160ps Any In-to-Out tpd
20ps typical tr/tf
Ultra-low jitter design:
0.2psRMS typical random jitter (data)
2psPP typical deterministic jitter (data)
5psPP typical total jitter (clock)
46fsRMS typical additive phase jitter (clock)
Unique input termination and VT pin accepts AC- and
DC-coupled inputs (CML, PECL)
Internal 50Ω output source termination
Typical 400mV CML output swing (RL = 50Ω)
Internal 50Ω input termination
Power supply 2.5V ±5% or 3.3V ±10%
–40°C to +85°C industrial temperature range
Available in a 16-pin 3mm × 3mm QFN package
Applications
Data communciation systems
OC-192, OC-192+FEC data-to-clock
All SONETOC-3 – OC-768 applications
Fibre Channel
Gigabit Ethernet
ATE
Test and measurement
AnyGate and Precision Edge are registered trademarks of Micrel, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
January 28, 2014
Revision 1.0
[email protected] or (408) 955-1690
1 page  
Micrel, Inc.
SY58051AU
CML Electrical Characteristics(10)
VCC = 2.5V ±5% or 3.3V ±10%; RL =100Ω across output pair or equivalent; TA = –40°C to +85°C.
Symbol Parameter
Condition
Min.
VOH
Output HIGH voltage
(Q, /Q)
RL = 50Ω to VCC
VCC-
0.020
VOUT
Output voltage swing
(Q, /Q)
See Figure 3
325
VDIFF_OUT
Differential output voltage swing
(Q, /Q)
See Figure 4
650
ROUT
Output source impedance
(Q, /Q)
45
Typ.
400
800
50
Max.
VCC
55
Units
V
mV
mV
Ω
AC Electrical Characteristics(10, 11)
VCC = 2.5V ±5% or 3.3V ±10%; RL =100Ω across output pair or equivalent; TA = –40°C to +85°C.
Symbol Parameter
Condition
Min. Typ. Max. Units
fMAX
Maximum operating frequency
Clock
NRZ data
8 GHz
10.7 Gbps
tpd
Propagation delay any input
(A, B, S)-to-Q
70 160 ps
tSKEW
Part-to-part skew
Data
Note 12
100 ps
tJITTER
Random jitter (RJ)
Deterministic jitter (DJ)
Clock
Cycle-to-cycle jitter (RJ)
Total jitter (TJ)
Additive phase jitter
Note 13
Note 14
Note 15
Note 16
622MHz input integrated over 12kHz – 20MHz
0.2 1 psRMS
2 5 psPP
0.5 1 psRMS
5 10 psPP
46 fsRMS
tr/tf
Output rise/fall times
(20% to 80%)
At full output swing
20 50
ps
Notes:
10. Specification for packaged product only.
11. Measured with 100mV input swing. See the Timing Diagrams section for definition of parameters. High-frequency AC parameters are guaranteed by
design and characterization.
12. Skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the respective inputs.
13. Random jitter is measured with a K28.7 comma detect character pattern, measured at 2.5Gbps/3.2Gbps.
14. Deterministic jitter is measured at 2.5Gbps/3.2Gbps with both K28.5 and 223–1 PRBS pattern.
15. Cycle-to-cycle jitter definition: the variation of periods between adjacent cycles, Tn – Tn–1 where Tn is the time between rising edges of the output
signal.
16. Total jitter definition: with an ideal clock input of frequency ≤fMAX, no more than one output edge in 1012 output edges will deviate by more than the
specified peak-to-peak jitter value.
January 28, 2014
5 Revision 1.0
[email protected] or (408) 955-1690
5 Page 
Micrel, Inc.
Input Interface Applications
SY58051AU
Figure 5. Static Input Level
Figure 6. LVDS Interface
(DC-Coupled)
Figure 7. LVDS Interface
(AC-Coupled)
Note: Be certain that the LVDS driver can be AC-coupled.
Figure 8. CML Interface
(DC-Coupled)
Figure 9. CML Interface
(AC-Coupled)
January 28, 2014
11 Revision 1.0
[email protected] or (408) 955-1690
11 Page | ||
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| PDF Descargar | [ Datasheet SY58051AU.PDF ] | |
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