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IDT82V2041E Schematic ( PDF Datasheet ) - IDT

Teilenummer IDT82V2041E
Beschreibung SINGLE CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
Hersteller IDT
Logo IDT Logo 




Gesamt 30 Seiten
IDT82V2041E Datasheet, Funktion
SINGLE CHANNEL T1/E1/J1
SHORT HAUL LINE INTER-
FACE UNIT
IDT82V2041E
FEATURES
• Single channel T1/E1/J1 short haul line interfaces
• Supports HPS (Hitless Protection Switching) for 1+1 protection
without external relays
• Programmable T1/E1/J1 switchability allowing one bill of ma-
terial for any line condition
• Single 3.3 V power supply with 5 V tolerance on digital interfaces
• Meets or exceeds specifications in
- ANSI T1.102, T1.403 and T1.408
- ITU I.431, G.703, G.736, G.775 and G.823
- ETSI 300-166, 300-233 and TBR12/13
- AT&T Pub 62411
• Software programmable or hardware selectable on:
- Wave-shaping templates
- Line terminating impedance (T1:100 , J1:110 Ω, E1:75 Ω/120 Ω)
- Adjustment of arbitrary pulse shape
- JA (Jitter Attenuator) position (receive path or transmit path)
- Single rail/dual rail system interfaces
- B8ZS/HDB3/AMI line encoding/decoding
- Active edge of transmit clock (TCLK) and receive clock (RCLK)
- Active level of transmit data (TDATA) and receive data (RDATA)
- Receiver or transmitter power down
- High impedance setting for line drivers
- PRBS (Pseudo Random Bit Sequence) generation and detection
with 215-1 PRBS polynomials for E1
- QRSS(QuasiRandomSequenceSignals) generationanddetection
with 220-1 QRSS polynomials for T1/J1
- 16-bit BPV (Bipolar Pulse Violation) /Excess Zero/PRBS or QRSS
error counter
- Analog loopback, Digital loopback, Remote loopback and Inband
loopback
• Adaptive receive sensitivity up to -20 dB (Host Mode only)
• Short circuit protection and internal protection diode for line
drivers
• LOS (Loss Of Signal) detection with programmable LOS levels
(Host Mode only)
• AIS (Alarm Indication Signal) detection
• Supports serial control interface, Motorola and Intel Multiplexed
interfaces and hardware control mode
• Pin compatibe to 82V2081 T1/E1/J1 Long Haul/Short Haul LIU
and 82V2051E E1 Short Haul LIU
• Package:
Available in 44-pin TQFP packages
Green package options available
DESCRIPTION
The IDT82V2041E can be configured as a single channel T1, E1 or J1
Line Interface Unit. The IDT82V2041E performs clock/data recovery, AMI/
B8ZS/HDB3 line decoding and detects and reports the LOS conditions. An
integrated Adaptive Equalizer is available to increase the receive sensitivity
and enable programming of LOS levels. In transmit path, there is an AMI/
B8ZS/HDB3 encoder and Waveform Shaper. There is one Jitter Attenua-
tor, which can be placed in either the receive path or the transmit path. The
Jitter Attenuator can also be disabled. The IDT82V2041E supports both
Single Rail and Dual Rail system interfaces. To facilitate the network main-
tenance, a PRBS/QRSS generation/detection circuit is integrated in the
chip, and different types of loopbacks can be set according to the applica-
tions. Four different kinds of line terminating impedance, 75 , 100 Ω, 110
and 120 are selectable. The chip also provides driver short-circuit pro-
tection and internal protection diode. The chip can be controlled by either
software or hardware.
The IDT82V2041E can be used in LAN, WAN, Routers, Wireless Base
Stations, IADs, IMAs, IMAPs, Gateways, Frame Relay Access Devices,
CSU/DSU equipment, etc.
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
2005 Integrated Device Technology, Inc.
1
December 9, 2005
DSC-6775/1






IDT82V2041E Datasheet, Funktion
IDT82V2041E
SINGLE CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
Table-42
Table-43
Table-44
Table-45
Table-46
Table-47
Table-48
Table-49
Table-50
Table-51
Table-52
Table-53
Table-54
Table-55
Table-56
Table-57
Table-58
Table-59
Table-60
Table-61
Table-62
Table-63
Table-64
Table-65
INTES: Interrupt Trigger Edge Select Register ............................................................. 49
STAT0: Line Status Register 0 (real time status monitor)............................................. 50
STAT1: Line Status Register 1 (real time status monitor)............................................. 51
INTS0: Interrupt Status Register 0 ................................................................................ 52
INTS1: Interrupt Status Register 1 ................................................................................ 53
CNT0: Error Counter L-byte Register 0......................................................................... 54
CNT1: Error Counter H-byte Register 1 ........................................................................ 54
Hardware Control Pin Summary ................................................................................... 55
Absolute Maximum Rating ............................................................................................ 57
Recommended Operation Conditions ........................................................................... 57
Power Consumption...................................................................................................... 58
DC Characteristics ........................................................................................................ 58
E1 Receiver Electrical Characteristics .......................................................................... 59
T1/J1 Receiver Electrical Characteristics...................................................................... 60
E1 Transmitter Electrical Characteristics ...................................................................... 61
T1/J1 Transmitter Electrical Characteristics.................................................................. 62
Transmitter and Receiver Timing Characteristics ......................................................... 63
Jitter Tolerance ............................................................................................................. 64
Jitter Attenuator Characteristics .................................................................................... 67
Serial Interface Timing Characteristics ......................................................................... 70
Multiplexed Motorola Read Timing Characteristics....................................................... 71
Multiplexed Motorola Write Timing Characteristics ....................................................... 72
Multiplexed Intel Read Timing Characteristics .............................................................. 73
Multiplexed Intel Write Timing Characteristics .............................................................. 74
List of Tables
6 December 9, 2005

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IDT82V2041E pdf, datenblatt
IDT82V2041E
SINGLE CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
Table-1 Pin Description (Continued)
Name Type Pin No.
Description
SDO O
23 SDO: Serial Data Output
In serial microcontroller interface mode, this signal is the output data of the serial interface. Configuration or Status data at SDO
pin is clocked out of the device on the falling edge of SCLK if SCLKE pin is high, or on the rising edge of SCLK if SCLKE pin
is low.
ACK ACK: Acknowledge Output
In Motorola parallel mode interface, the low level on this pin means:
• The valid information is on the data bus during a read operation.
• The write data has been accepted during a write cycle.
RDY RDY: Ready signal output
In Intel parallel mode interface, the low level on this pin means a read or write operation is in progress; a high acknowledges
a read or write operation has been completed.
TERM
I
SCLKE
I
TERM: Internal or external termination select in hardware mode
This pin selects internal or external impedance matching for both receiver and transmitter.
• 0 = ternary interface with external impedance matching network
• 1 = ternary interface with internal impedance matching network
22 SCLKE: Serial Clock Edge Select
In serial microcontroller interface mode, this signal selects the active edge of SCLK for outputting SDO. The output data is valid
after some delay from the active clock edge. It can be sampled on the opposite edge of the clock. The active clock edge which
clocks the data out of the device is selected as shown below:
SCLKE
Low
High
SCLK
Rising edge is the active edge.
Falling edge is the active edge.
RD
DS
MONT
AD7 I/O
PULS3
I
RD: Read Strobe
In Intel parallel multiplexed interface mode, the data is driven to AD[7:0] by the device during low level of RD in a read operation.
DS: Data Strobe
In Motorola parallel multiplexed interface mode, this signal is the data strobe of the parallel interface. In a write operation (R/
W = 0), the data on AD[7:0] is sampled into the device. In a read operation (R/W = 1), the data is driven to AD[7:0] by the device.
MONT: Receive Monitor gain select
In hardware control mode with ternary interface, this pin selects the receive monitor gain of receiver:
0= 0 dB
1= 26 dB
33 AD7: Address/Data Bus bit7
In Intel/Motorola multiplexed interface mode, this signal is the multiplexed bi-directional address/data bus of the microcontroller
interface.
In serial microcontroller interface mode, this pin should be connected to ground through a 10 kresistor.
PULS[3:0]: these pins are used to select the following functions in hardware control mode:
• T1/J1/E1 mode
• Transmit pulse template
• Internal termination impedance (75/120/100/110)
Refer to 5 Hardware Control Pin Summary for details.
Pin Description
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