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PDF IDT82V2052E Data sheet ( Hoja de datos )
| Número de pieza | IDT82V2052E | |
| Descripción | DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT | |
| Fabricantes | IDT | |
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DUAL CHANNEL E1
SHORT HAUL LINE INTERFACE UNIT
IDT82V2052E
FEATURES:
• Dual channel E1 short haul line interfaces
• Supports HPS (Hitless Protection Switching) for 1+1 protection
without external relays
• Single 3.3 V power supply with 5 V tolerance on digital interfaces
• Meets or exceeds specifications in
- ANSI T1.102
- ITU I.431, G.703, G.736, G.775 and G.823
- ETSI 300-166, 300-233 and TBR12/13
• Software programmable or hardware selectable on:
- Wave-shaping templates
- Line terminating impedance (E1: 75 Ω/120 Ω)
- Adjustment of arbitrary pulse shape
- JA (Jitter Attenuator) position (receive path or transmit path)
- Single rail/dual rail system interfaces
- HDB3/AMI line encoding/decoding
- Active edge of transmit clock (TCLK) and receive clock (RCLK)
- Active level of transmit data (TDATA) and receive data (RDATA)
- Receiver or transmitter power down
- High impedance setting for line drivers
- PRBS (Pseudo Random Bit Sequence) generation and detection
with 215-1 PRBS polynomials
- 16-bit BPV (Bipolar Pulse Violation) / Excess Zero/ PRBS error
counter
- Analog loopback, Digital loopback, Remote loopback
• Adaptive receive sensitivity up to -20 dB (Host Mode only)
• Non-intrusive monitoring per ITU G.772 specification
• Short circuit protection and internal protection diode for line
drivers
• LOS (Loss Of Signal) detection with programmable LOS levels
(Host Mode only)
• AIS (Alarm Indication Signal) detection
• JTAG interface
• Supports serial control interface, Motorola and Intel Non-Multi-
plexed interfaces and hardware control mode
• Pin compatible to 82V2082 T1/E1/J1 Long Haul/Short Haul LIU
and 82V2042E T1/E1/J1 Short Haul LIU
• Available in 80-pin TQFP
Green package options available
DESCRIPTION:
The IDT82V2052E is a dual channel E1 Line Interface Unit. The
IDT82V2052E performs clock/data recovery, AMI/HDB3 line decoding and
detects and reports the LOS conditions. An integrated Adaptive Equalizer
is available to increase the receive sensitivity and enable programming of
LOS levels. In transmit path, there is an AMI/HDB3 encoder and Waveform
Shaper. There is one Jitter Attenuator, which can be placed in either the
receive path or the transmit path. The Jitter Attenuator can also be disabled.
The IDT82V2052E supports both Single Rail and Dual Rail system inter-
faces. To facilitate the network maintenance, a PRBS generation/detection
circuit is integrated in the chip, and different types of loopbacks can be set
according to the applications. Two different kinds of line terminating imped-
ance, 75 Ω and 120 Ω are selectable on a per channel basis. The chip also
provides driver short-circuit protection and internal protection diode and
supports JTAG boundary scanning. The chip can be controlled by either
software or hardware.
The IDT82V2052E can be used in LAN, WAN, Routers, Wireless Base
Stations, IADs, IMAs, IMAPs, Gateways, Frame Relay Access Devices,
CSU/DSU equipment, etc.
.IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
2005 Integrated Device Technology, Inc.
1
December 12, 2005
DSC-6779/1
1 page  
List of Tables
Table-1
Table-2
Table-3
Table-4
Table-5
Table-6
Table-7
Table-8
Table-9
Table-10
Table-11
Table-12
Table-13
Table-14
Table-15
Table-16
Table-17
Table-18
Table-19
Table-20
Table-21
Table-22
Table-23
Table-24
Table-25
Table-26
Table-27
Table-28
Table-29
Table-30
Table-31
Table-32
Table-33
Table-34
Table-35
Table-36
Table-37
Table-38
Table-39
Table-40
Table-41
Pin Description ................................................................................................................ 9
Transmit Waveform Value For E1 75 Ohm ................................................................... 19
Transmit Waveform Value For E1 120 Ohm ................................................................. 19
Impedance Matching for Transmitter ............................................................................ 20
Impedance Matching for Receiver ................................................................................ 21
Criteria of Starting Speed Adjustment........................................................................... 24
LOS Declare and Clear Criteria, Adaptive Equalizer Disabled ..................................... 25
LOS Declare and Clear Criteria, Adaptive Equalizer Enabled ...................................... 26
AIS Condition ................................................................................................................ 26
Criteria for Setting/Clearing the PRBS_S Bit ................................................................ 27
EXZ Definition ............................................................................................................... 30
Interrupt Event............................................................................................................... 34
Global Register List and Map........................................................................................ 36
Per Channel Register List and Map .............................................................................. 37
ID: Device Revision Register ........................................................................................ 38
RST: Reset Register ..................................................................................................... 38
GCF: Global Configuration Register ............................................................................. 38
INTCH: Interrupt Channel Indication Register............................................................... 38
TERM: Transmit and Receive Termination Configuration Register .............................. 39
JACF: Jitter Attenuation Configuration Register ........................................................... 39
TCF0: Transmitter Configuration Register 0 ................................................................. 40
TCF1: Transmitter Configuration Register 1 ................................................................. 40
TCF2: Transmitter Configuration Register 2 ................................................................. 41
TCF3: Transmitter Configuration Register 3 ................................................................. 41
TCF4: Transmitter Configuration Register 4 ................................................................. 41
RCF0: Receiver Configuration Register 0..................................................................... 42
RCF1: Receiver Configuration Register 1..................................................................... 42
RCF2: Receiver Configuration Register 2..................................................................... 43
MAINT0: Maintenance Function Control Register 0...................................................... 43
MAINT1: Maintenance Function Control Register 1...................................................... 44
MAINT6: Maintenance Function Control Register 6...................................................... 44
INTM0: Interrupt Mask Register 0 ................................................................................. 45
INTM1: Interrupt Masked Register 1 ............................................................................. 45
INTES: Interrupt Trigger Edge Select Register ............................................................. 46
STAT0: Line Status Register 0 (real time status monitor)............................................. 47
STAT1: Line Status Register 1 (real time status monitor)............................................. 48
INTS0: Interrupt Status Register 0 ................................................................................ 48
INTS1: Interrupt Status Register 1 ................................................................................ 49
CNT0: Error Counter L-byte Register 0......................................................................... 49
CNT1: Error Counter H-byte Register 1 ........................................................................ 49
Hardware Control Pin Summary ................................................................................... 50
List of Tables
5 December 12, 2005
5 Page 
IDT82V2052E
DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
Table-1 Pin Description (Continued)
Name
MODE1
MODE0
Type
I
Pin No.
9
10
Description
MODE[1:0]: operation mode of control interface select
The level on this pin determines which control mode is used to control the device as follows:
RCLKE
I
RXTXM1
RXTXM0
I
CS I
LP11
INT O
LP10
I
MODE[1:0]
00
01
10
11
Control Interface mode
Hardware interface
Serial Microcontroller Interface
Motorola non-multiplexed
Intel non-multiplexed
• The serial microcontroller interface consists of CS, SCLK, SCLKE, SDI, SDO and INT pins. SCLKE is used for the
selection of the active edge of SCLK.
• The parallel non-multiplexed microcontroller interface consists of CS, A[5:0], D[7:0], DS/RD, R/W/WR and INT pins.
(Refer to 3.11 MICROCONTROLLER INTERFACES for details)
• Hardware interface consists of PULSn, THZ, RCLKE, LPn[1:0], PATTn[1:0], JA[1:0], MONTn, TERMn, RPDn,
MODE[1:0] and RXTXM[1:0] (n=1, 2).
11 RCLKE: the active edge of RCLKn select
In hardware control mode, this pin selects the active edge of RCLKn
• L= update RDPn/RDNn on the rising edge of RCLKn
• H= update RDPn/RDNn on the falling edge of RCLKn
In software control mode, this pin should be connected to GNDIO.
14 RXTXM[1:0]: Receive and transmit path operation mode select
15 In hardware control mode, these pins are used to select the single rail or dual rail operation modes as well as AMI or HDB3
line coding:
• 00= single rail with HDB3 coding
• 01= single rail with AMI coding
• 10= dual rail interface with CDR enabled
• 11= slicer mode (dual rail interface with CDR disabled)
In software control mode, these pins should be connected to ground.
42 CS: Chip Select
In serial or parallel microcontroller interface mode, this is the active low enable signal. A low level on this pin enables serial
or parallel microcontroller interface.
LP11/LP10: Loopback mode select for channel 1
When the chip is configured by hardware, this pin is used to select loopback operation modes for channel 1.:
• 00 = no loopback
• 01 = analog loopback
• 10 = digital loopback
• 11 = remote loopback
41 INT: Interrupt Request
In software control mode, this pin outputs the general interrupt request for all interrupt sources. If INTM_GLB bit (GCF, 20H)
is set to ‘1’, all the interrupt sources will be masked. These interrupt sources can be masked individually via registers (INTM0,
13H...) and (INTM1, 14H...). The interrupt status is reported via the registers (INTCH, 21H), (INTS0, 18H...) and (INTS1,
19H...).
Output characteristics of this pin can be defined to be push-pull (active high or active low) or open-drain (active low) by setting
bits INT_PIN[1:0] (GCF, 20H)
LP11/LP10: Loopback mode select for channel 1
See above LP11.
PIN DESCRIPTION
11 December 12, 2005
11 Page | ||
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