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IDT82V2048 Schematic ( PDF Datasheet ) - IDT

Teilenummer IDT82V2048
Beschreibung OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT
Hersteller IDT
Logo IDT Logo 




Gesamt 30 Seiten
IDT82V2048 Datasheet, Funktion
OCTAL T1/E1 SHORT HAUL
LINE INTERFACE UNIT
IDT82V2048
FEATURES
Fully integrated octal T1/E1 short haul line interface which
supports 100T1 twisted pair, 120E1 twisted pair and 75
E1 coaxial applications
Selectable single rail or dual rail mode and AMI or HDB3/B8ZS
line encoder/decoder
Built-in transmit pre-equalization meets G.703 & T1.102
Selectable transmit/receive jitter attenuator meets ETSI CTR12/
13, ITU G.736, G.742,G.823 and AT&T Pub 62411 specifications
SONET/SDH optimized jitter attenuator meets ITU G.783 map-
ping jitter specification
Digital/analog LOS detector meets ITU G.775, ETS 300 233 and
T1.231
ITU G.772 non-intrusive monitoring for in-service testing for
any one of channel1 to channel7
Low impedance transmit drivers with tri-state
Selectable hardware and parallel/serial host interface
Local, remote and inband loopback test functions
Hitless Protection Switching (HPS) for 1 to 1 protection with-
out relays
JTAG boundary scan for board test
3.3V supply with 5V tolerant I/O
Low power consumption
Operating Temperature Range: -40°C to +85°C
Available in 144-pin Thin Quad Flat Pack (TQFP_144_DA) and
160-pin Plastic Ball Grid Array (PBGA) packages
FUNCTIONAL BLOCK DIAGRAM
RTIPn
RRINGn
TTIPn
TRINGn
G.772
Monitor
Analog
Peak
Loopback Detector
Line
Driver
Clock
Generator
Slicer
LOS
Detector
CLK&Data
Recovery
(DPLL)
Digital
Loopback
Waveform
Shaper
Transmit
All Ones
One of Eight Identical Channels
Jitter
Attenuator
B8ZS/
HDB3/AMI
Decoder
Remote
Loopback
IBLC
Detector
AIS
Detector
Jitter
Attenuator
B8ZS/
HDB3/AMI
Encoder
IBLC
Generator
LOSn
RCLKn
RDn/RDPn
CVn/RDNn
TCLKn
TDn/TDPn
BPVIn/TDNn
Control Interface
Register
File
JTAG TAP
VDD IO
VDDT
VDDD
VDDA
Figure - 1. Block Diagram
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGES
© 2003 Integrated Device Technology, Inc.
1
DECEMBER 2003
DSC-6037/11






IDT82V2048 Datasheet, Funktion
IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
PIN DESCRIPTION (CONTINUED)
Name
Type
Pin No.
QFP144 BGA160
Description
RD0/RDP0 O
40 P2 RDn: Receive Data for Channel 0~7
RD1/RDP1
33 M2 In Single Rail Mode, the received NRZ data is output on this pin. The data is decoded by AMI or
RD2/RDP2 Tri-state 77
M13 HDB3/B8ZS line code rule.
RD3/RDP3
70 P13
RD4/RDP4
111 A13 CVn: Code Violation for Channel 0~7
RD5/RDP5
104 C13 In Single Rail Mode, the bipolar violation, code violation and excessive zeros will be reported by driving
RD6/RDP6
5 C2 pin CVn to high level for a full clock cycle. However, only bipolar violation is indicated when AMI
RD7/RDP7
142 A2 decoder is selected.
CV0/RDN0
CV1/RDN1
CV2/RDN2
CV3/RDN3
CV4/RDN4
CV5/RDN5
CV6/RDN6
CV7/RDN7
41
34
76
69
112
105
4
141
RCLK0
RCLK1
RCLK2
RCLK3
RCLK4
RCLK5
RCLK6
RCLK7
MCLK
O
Tri-state
I
39
32
78
71
110
103
6
143
10
LOS0
O
42
LOS1
35
LOS2
75
LOS3
68
LOS4
113
LOS5
106
LOS6
3
LOS7
140
P3 RDPn/RDNn: Positive/Negative Receive Data for Channel 0~7
M3 In Dual Rail Mode with clock recovery, these pins output the NRZ data. A high signal on RDPn
M12 indicates the receipt of a positive pulse on RTIPn/RRINGn while a high signal on RDNn indicates the
P12 receipt of a negative pulse on RTIPn/RRINGn.
A12 The output data at RDn or RDPn/RDNn are valid on the falling edges of RCLK when the CLKE input is
C12 in High level, or valid on the rising edges of RCLK when CLKE is Low.
C3 In Dual Rail Mode without clock recovery, these pins output ht e raw RZ sliced data. In this data
A3 recovery mode, the active polarity of RDPn/RDNn is determined by pin CLKE. When pin CLKE is Low,
RDPn/RDNn is active low. When pin CLKE is High, RDPn/RDNn is active high.
In hardware mode, RDn or RDPn/RDNn will remain active during LOS. In host mode, these pins will
either remain active or insert alarm indication signal (AIS) into the receive path, determined by bit AISE
in register GCF (Global Configuration register).
RDn or RDPn/RDNn is set into high impedance when the corresponding receiver is power down.
P1 RCLKn: Receive Clock for Channel 0~7
M1 In clock recovery mode, this pin outputs the recovered clock from signal received on RTIPn/RRINGn.
M14 The received data are clocked out of the device on rising edges of RCLKn if pin CLKE is low, or on
P14 falling edges of RCLKn if pin CLKE is high.
A14 In data recovery mode, RCLKn is the output of an internal exclusive OR (XOR) which is connected with
C14 RDPn and RDNn. The clock is recovered from the signal on RCLKn externally.
C1 If receiver n is power down, the corresponding RCLKn is in high impedance.
A1
E1 MCLK: Master Clock
This is the independent, free running reference clock. A clock of 1.544 MHz (for T1 mode) or 2.048
MHz (for E1 mode) is supplied to this pin as the clock reference of the device for normal operation.
In receive path, when MCLK is high, the device slices the incoming bipolar line signal into RZ pulse
(Data Recovery mode). When MCLK is low, all the receivers are power down, and the output pins
RCLKn, RDPn and RDNn are switched to high impedance.
In transmit path, the operation mode is decided by the combination of MCLK and TCLKn (see TCLKn
pin description for detail).
Note that wait state generation via RDY/ACK is not available if MCLK is not provided.
K4 LOSn: Loss of Signal Output for Channel 0~7
K3 A high level on this pin indicates the loss of signal when there is no transition over a specified period of
K12 time and no enough ones density in the received signal. The transition will return to low automatically
K11 when there is enough transitions over a specified period of time with a certain ones density in the
E11 received signal. The LOS assertion and desertion criteria are described in the Functional Description.
E12
E3
E4
6

6 Page









IDT82V2048 pdf, datenblatt
IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
FUNCTIONAL DESCRIPTION
OVERVIEW
The IDT82V2048 is a fully integrated octal short-haul line interface
unit, which contains eight transmit and receive channels for use in either
E1 or T1 applications. The receiver performs clock and data recovery.
As an option, the raw sliced data (no retiming) can be output to the sys-
tem. Transmit equalization is implemented with low-impedance output
drivers that provide shaped waveforms to the transformer, guaranteeing
template conformance. A selectable jitter attenuation may be placed in
the receive path or the transmit path. Moreover, multiple testing func-
tions, such as error detection, loopback and JTAG boundary scan are
also provided. The device is optimized for flexible software control
through a serial or parallel host mode interface. Hardware control is also
available. Figure-1 shows One of the Eight Identical Channels operation.
T1 / E1 MODE SELECTION
T1/E1 mode selection configures the device globally. In Hardware
Mode, the template selection pins: TS2, TS1 and TS0 determine
whether the operation mode is T1 or E1 (refer to Table-7). In Software
Mode, the Transmit Template Select Register (Primary Register: 11Hex)
determines whether the operation mode is T1 or E1.
SYSTEM INTERFACE
The system interface of each channel can be configured to operate
in different modes:
1. Single Rail interface with clock recovery.
2. Dual Rail interface with clock recovery.
3. Dual Rail interface with data recovery (that is, with raw data slicing
only and without clock recovery).
Therefore, each signal pin on system side has multiple functions
depending on which operation mode the device is in.
The Dual Rail interface consists of TDPn1, TDNn, TCLKn, RDPn,
RDNn and RCLKn. Data transmitted from TDPn and TDNn appears on
TTIPn and TRINGn at the line interface; data received from the RTIPn
and RRINGn at the line interface are transferred to RDPn and RDNn
while the recovered clock extracting from the received data stream
outputs on RCLKn. In Dual Rail operation, the clock/data recovery mode
is selectable. Dual Rail interface with clock recovery shown in Figure-3
is a default configuration mode. Dual Rail interface with data recovery is
shown in Figure-4. Pin RDPn and RDNn, in this condition, are raw RZ
slice output and internally connected to an EXOR which is fed to the
RCLKn output for external clock recovery applications.
In Single Rail Mode, data transmitted from TDn appears on TTIPn
and TRINGn at the line interface. Data received from the RTIPn and
RRINGn at the line interface appears on RDn while the recovered clock
extracting from the received data stream outputs on RCLKn. When the
device is in single rail interface, the selectable AMI or HDB3/B8ZS line
encoder/decoder is available and any code violation in the received data
will be indicated at the CVn pin. The Single Rail Mode can be devided
into 2 sub-modes. Single Rail Mode 1, whose interface is composed of
TDn, TCLKn, RDn, CVn and RCLKn, is realized by pulling pin TDNn to
high for more than 16 consecutive TCLK cycles. Single Rail Mode 2,
whose interface is composed of TDn, TCLKn, RDn, CVn, RCLKn and
BPVIn, is realized by setting bit CRS in e-CRS2 and bit SING in e-SING.
The difference between them is that, in the latter mode bipolar violation
can be inserted via pin BPVIn if AMI line code is selected.
The configuration of different system interface is summarized in
Table-1.
RTIPn
RRINGn
TTIPn
TRINGn
Slicer
Peak
Detector
Line
Driver
LOS
Detector
CLK&Data
Recovery
(DPLL)
One of Eight Identical Channels
Jitter
Attenuator
B8ZS/
HDB3/AMI
Decoder
Waveform
Shaper
Transmit
All Ones
Jitter
Attenuator
B8ZS/
HDB3/AMI
Encoder
Figure - 3. Dual Rail Interface with Clock Recovery 3
NOTE:
1. The footprint ‘n’ (n = 0 - 7) indicates one of the eight channels
2. The first letter “e-”indicates expanded register.
3. The grey blocks are bypassed and the dotted blocks are selectable
12
LOSn
RCLKn
RDPn
RDNn
TCLKn
TDPn
TDNn

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