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PDF APA3175 Data sheet ( Hoja de datos )
| Número de pieza | APA3175 | |
| Descripción | 20W Stereo Digital Class-D Audio Power Amplifier | |
| Fabricantes | ANPEC | |
| Logotipo |  |
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APA3175
20W Stereo Digital Class-D Audio Power Amplifier with EQ and DRC
Features
General Description
• Operating Voltage: 4.5V~24V for PVDD
The APA3175 is a digital input, stereo, high efficiency,
– 3.0V~3.6V for DVDD and AVDD
• High Efficiency Class-D Operation Eliminate the
Class-D audio amplifier available in a TQFP7x7-48P
package.
Need of Heatsinks
The APA3175 accepts the digital serial audio data and
• Digital Serial Audio Input (Stereo Output)
using the digital audio processor to convert the audio
• I2C Control Interface
data becomes the stereo Class-D output speaker
• Sampling Rate can Support from 32kHz to 192kHz amplifier. This provides the seamless integration between
• Separated Volume Control from 24dB to Mute
the codec and the speaker amplifier.
• Soft Mute (50% Duty Cycle)
The APA3175 is a slave device receiving clocks from ex-
• Programmable Dynamic Range Compression
ternal source, and the Class-D’s PWM switching fre-
– Power Limiter
quency is 352.8kHz for the sampling rate 44.1kHz or 384
– Speaker Protection
kHz for sampling 48kHz, depend on the input signal’s
– Night-Mode Listening
sampling rate.
• Programmable Biquads for Speaker EQ
• Shutdown and Mute Function
Pin Configuration
• Thermal and Over-Current Protections with Auto-
Recovery
• Space Saving Package TQFP7x7-48P
• Lead Free and Green Devices Available
(RoHS Compliant)
Applications
• LCD TV
Simplified Application Circuit
OUT_A 1
PVDD_A 2
PVDD_A 3
ABS 4
GDREG 5
NC 6
NC 7
TM 8
AVSS 9
PLL_LF 10
NC 11
NC 12
TOP VIEW
(APA3175)
36 OUT_D
35 PVDD_D
34 PVDD_D
33 DBS
32 GDREG
31 DVREG
30 AGND
29 GND
28 DVSS
27 DVDD
26 TP3
25 /RST
Digital Audio
Source
I2C
Control
MCLK
LRCLK
SCLK
SDIN
OUT_A
OUT_B
APA3175
SDA
SCL
OUT_C
OUT_D
Left
Channel
Speaker
Right
Channel
Speaker
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright © ANPEC Electronics Corp.
Rev. A.3 - Aug., 2016
1
www.anpec.com.tw
1 page  
APA3175
Electrical Characteristics (Cont.)
TA=25οC, PVDD=18V, VDD=3.3V (AVDD and DVDD), RL=8Ω, BD Mode, fS=48kHz (unless otherwise noted)
Symbol
Parameter
AC CHARACTERISTICS
S/N Signal to Noise Ratio
Test Conditions
RL=8Ω, PO=16W, With
A-Weighting Filter (AV=0dB)
Min.
APA3175
Typ.
Max.
- 97 -
Vn Noise Output Voltage
With A-Weighting Filter (AV=0dB)
-
150
-
Unit
dB
µVrms
Serial Audio Ports Slave Mode
Over recommended operating conditions (unless otherwise noted)
Symbol
Parameter
Test Conditions
APA3175
Min.
Typ.
Max.
Unit
Vn
fSCLK
tSetup1
tHold1
Noise Output Voltage
Frequency, SCLK 32xfS, 48xfS,
64xfS
Setup Time, LRCLK to SCLK
Rising Edge
Hold Time, LRCLK to SCLK
Rising Edge
With A-Weighting Filter (AV=0dB)
-
CL=30pF
1.024
10
10
150 - µVrms
- 12.288 MHz
--
ns
--
Serial Audio Ports Slave Mode
Over recommended operating conditions (unless otherwise noted)
Symbol
Parameter
tSetup2
Setup Time, SDIN to SCLK
Rising Edge
tHold
Hold Time, SDIN to SCLK Rising
Edge
LRCLK Frequency
LRCLK Duty Cycle
SCLK Duty Cycle
SCLK Rising Edges Between
LRCLK Riding Edges
t(edge)
LRCLK Clock Edge With Respect
To The Falling Edge of SCLK
tr/tf Rise/Fall Time for SCLK/LRCLK
(SCLK/LRCLK)
Reset Timing
Test Conditions
APA3175
Min.
Typ.
Max.
10 -
-
10 -
-
8K 48K 48K
40 50 60
40 50 60
32 - 64
-1/4 - 1/4
- -8
Unit
ns
kHz
%
SCLK
edges
SCLK
period
ns
Control signal parameters over recommended operating conditions (unless otherwise noted). Please refer to “Rec-
ommended Use Model” section on usage of all terminals.
Symbol
Parameter
tp(RST)
td(12C_Ready)
Pulse Duration, RST Active.
Time to Enable I2C
Test Conditions
No Load
Min.
100
-
APA3175
Typ.
-
-
Max.
-
13.5
Unit
µs
ms
Copyright © ANPEC Electronics Corp.
Rev. A.3 - Aug., 2016
5
www.anpec.com.tw
5 Page 
APA3175
Pin Description (Cont.)
PIN
NO. NAME
44, 45
PVDD_B
46 OUT_B
47, 48
PGND_AB
I/O/P
FUNCTION
P Power supply for half bridge B.
O Output of half bridge B.
P Power Ground connection for half bridge A and B.
Block Diagram
DVDD
1V8_DV
SDIN
DGND
MCLK
SCLK
LRCLK
Regulator
3.3V to 1.8V
Serial
Audio
Port
EQ 7XBQ
EQ 7XBQ
DRC &
Volume
Sampling
Rate
Inter
Polarization
Fifth Order
Noise
Shaper and
PWM
PLL_LF
PLL
Central Control
Half Bridge
A FET
Output
Half Bridge
B FET
Output
Half Bridge
C FET
Output
Half Bridge
D FET
Output
SDA
SCL
AGND
Serial Control
Register
Bank
control logic
Regulator
3.3V to 1.8V
RST SD ERROR 1V8_AV AVDD
Analog
Power
Stage
PVDD_A
BS_A
OUT_A
PGND_A
PGND_B
OUT_B
BS_B
PVDD_B
VCMP_AB
VCMP_CD
PVDD_C
BS_C
OUT_C
PGND_C
PGND_D
OUT_D
BS_D
PVDD_D
AVCC
BYPASS
AVSS
Copyright © ANPEC Electronics Corp.
Rev. A.3 - Aug., 2016
11
www.anpec.com.tw
11 Page | ||
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