Datenblatt-pdf.com


8T49N283 Schematic ( PDF Datasheet ) - IDT

Teilenummer 8T49N283
Beschreibung NG Octal Universal Frequency Translator
Hersteller IDT
Logo IDT Logo 




Gesamt 30 Seiten
8T49N283 Datasheet, Funktion
FemtoClock® NG Octal Universal
Frequency Translator
8T49N283
Datasheet
General Description
The 8T49N283 has two independent, fractional-feedback PLLs that
can be used as jitter attenuators and frequency translators. It is
equipped with six integer and two fractional output dividers, allowing
the generation of up to 8 different output frequencies, ranging from
8kHz to 1GHz. Four of these frequencies are completely
independent of each other and the inputs. The other four are related
frequencies. The eight outputs may select among LVPECL, LVDS or
LVCMOS output levels.
This makes it ideal to be used in any frequency translation
application, including 1G, 10G, 40G and 100G Synchronous
Ethernet, OTN, and SONET/SDH, including ITU-T G.709 (2009) FEC
rates. The device may also behave as a frequency synthesizer.
The 8T49N283 accepts up to two differential or single-ended input
clocks and a crystal input. Each of the two internal PLLs can lock to
different input clocks which may be of independent frequencies. Each
PLL can use the other input for redundant backup of the primary
clock, but in this case, both input clocks must be related in frequency.
The device supports hitless reference switching between input
clocks. The device monitors all input clocks for Loss of Signal (LOS),
and generates an alarm when an input clock failure is detected.
Automatic and manual hitless reference switching options are
supported. LOS behavior can be set to support gapped or un-gapped
clocks.
The 8T49N283 supports holdover for each PLL. The holdover has an
initial accuracy of ±50ppB from the point where the loss of all
applicable input reference(s) has been detected. It maintains a
historical average operating point for each PLL that may be returned
to in holdover at a limited phase slope.
The device places no constraints on input to output frequency
conversion, supporting all FEC rates, including the new revision of
ITU-T Recommendation G.709 (2009), most with 0ppm conversion
error.
Each PLL has a register-selectable loop bandwidth from 0.5Hz to
512Hz.
Each output supports individual phase delay settings to allow
output-output alignment.
The device supports Output Enable inputs and Lock, Holdover and
LOS status outputs.
The device is programmable through an I2C interface. It also
supports I2C master capability to allow the register configuration to
be read from an external EEPROM.
Applications
OTN or SONET / SDH equipment Line cards (up to OC-192, and
supporting FEC ratios)
OTN de-mapping (Gapped Clock and DCO mode)
Gigabit and Terabit IP switches / routers including support of
Synchronous Ethernet
Wireless base station baseband
Data communications
Features
Supports SDH/SONET and Synchronous Ethernet clocks
including all FEC rate conversions
Two differential outputs meet jitter limits for 100G Ethernet and
STM-256/OC-768
<0.3ps RMS (including spurs): 12kHz to 20MHz
All outputs <0.5ps RMS (including spurs) 12kHz to 20MHz
Operating modes: locked to input signal, holdover and free-run
Initial holdover accuracy of ±50ppb
Accepts up to two LVPECL, LVDS, LVHSTL or LVCMOS input
clocks
Accepts frequencies ranging from 8kHz up to 875MHz
Auto and manual input clock selection with hitless switching
Clock input monitoring, including support for gapped clocks
Phase-Slope Limiting and Fully Hitless Switching options to
control output phase transients
Operates from a 10MHz to 40MHz fundamental-mode crystal
Generates eight LVPECL / LVDS or sixteen LVCMOS output
clocks
Output frequencies ranging from 8kHz up to 1.0GHz (diff)
Output frequencies ranging from 8kHz to 250MHz (LVCMOS)
Four General Purpose I/O pins with optional support for status &
control:
Four Output Enable control inputs may be mapped to any of the
eight outputs
Lock, Holdover & Loss-of-Signal status outputs
Open-drain Interrupt pin
Programmable PLL bandwidth settings for each PLL:
0.5Hz, 1Hz, 2Hz, 4Hz, 8Hz, 16Hz, 32Hz, 64Hz, 128Hz, 256Hz
or 512Hz
Optional Fast Lock function
Programmable output phase delays in steps as small as 16ps
Register programmable through I2C or via external I2C EEPROM
Bypass clock paths for system tests
Power supply modes
VCC / VCCA / VCCO
3.3V / 3.3V / 3.3V
3.3V / 3.3V / 2.5V
3.3V / 3.3V / 1.8V (LVCMOS)
2.5V / 2.5V / 3.3V
2.5V / 2.5V / 2.5V
2.5V / 2.5V / 1.8V (LVCMOS)
Power down modes support consumption as low as 1.7W (see
Section, “Power Dissipation and Thermal Considerations” for
details)
-40°C to 85°C ambient operating temperature
Package: 56QFN, lead-free (RoHS 6)
©2016 Integrated Device Technology, Inc.
1
Revision H, October 26, 2016






8T49N283 Datasheet, Funktion
8T49N283 Datasheet
Principles of Operation
The 8T49N283 has two PLLs that can each independently be locked
to any of the input clocks and generate a wide range of synchronized
output clocks.
It incorporates two completely independent PLLs. These could be
used for example in the transmit and receive path of Synchronous
Ethernet equipment. Either of the input clocks can be selected as the
reference for either PLL. From the output of the two PLLs a wide
range of output frequencies can be simultaneously generated.
The 8T49N283 accepts up to two differential input clocks ranging
from 8kHz up to 875MHz. It generates up to eight output clocks
ranging from 8kHz up to 1.0GHz.
Each PLL path within the 8T49N283 supports three states: Lock,
Holdover and Free-run. Lock & holdover status may be monitored on
register bits and pins. Each PLL also supports automatic and manual
hitless reference switching. In the locked state, the PLL locks to a
valid clock input and its output clocks have a frequency accuracy
equal to the frequency accuracy of the input clock. In the Holdover
state, the PLL will output a clock which is based on the selected
holdover behavior. Each of the PLL paths within the 8T49N283 has
an initial holdover frequency offset of ±50ppb. In the Free-run state,
the PLL outputs a clock with the same frequency accuracy as the
external crystal.
Upon power up, each PLL will enter Free-run state, in this state it
generates output clocks with the same frequency accuracy as the
external crystal. The 8T49N283 continuously monitors each input for
activity (signal transitions).
In automatic reference switching, when an input clock has been
validated the PLL will transition to the locked state. If the selected
input clock fails and there are no other valid input clocks, the PLL will
quickly detect that and go into holdover. In the Holdover state, the
PLL will output a clock which is based on the selected holdover
behavior. If the selected input clock fails and another input clock is
available then the 8T49N283 will hitlessly switch to that input clock.
The reference switch can be either revertive or non-revertive.
The device supports conversion of any input frequency to four
different, independent output frequencies on the Q[0:3]outputs.
Additionally, a further four output frequencies may be generated that
are integer-related to the four independent frequencies. These
additional four frequencies are on the Q[4:7] outputs.
The 8T49N283 has a programmable loop bandwidth from 0.5Hz to
512Hz.
The device monitors all input clocks and generates an alarm when an
input clock failure is detected.
The device supports programmable individual output phase
adjustments in order to allow control of input to output phase
adjustments and output to output phase alignment.
The device is programmable through an I2C and may also
autonomously read its register settings from an internal One-Time
Programmable (OTP) memory or an external serial I2C EEPROM.
Crystal Input
The crystal input on the 8T49N283 is capable of being driven by a
parallel-resonant, fundamental mode crystal with a frequency range
of 10MHz - 40MHz.
The oscillator input also supports being driven by a single-ended
crystal oscillator or reference clock.
The initial holdover frequency offset is set by the device, but the long
term drift depends on the quality of the crystal or oscillator attached
to this port.
Bypass Path
For system test purposes, each of PLL0 and PLL1 may be bypassed.
When PLL_BYP is asserted the CLK0 input reference will be
presented directly on the Q4 output. The CLK1 input reference will be
presented directly on the Q5 output.
Additionally, CLK0 or CLK1 may be used as a clock source for the
output dividers of Q[4:7]. This may only be done for input frequencies
of 250MHz or less.
Input Clock Selection
The 8T49N283 accepts up to two input clocks with frequencies
ranging from 8kHz up to 875MHz. Each input can accept LVPECL,
LVDS, LVHSTL, HCSL or LVCMOS inputs using 1.8V, 2.5V or 3.3V
logic levels. To use LVCMOS inputs, refer to the Application Note,
Section, “Wiring the Differential Input to Accept Single-Ended Levels”
for biasing instructions.
The device has independent input clock selection control for each
PLL. In Manual mode, only one of these inputs may be chosen per
PLL and if that input fails that PLL will enter holdover.
Manual mode may be operated by directly selecting the desired input
reference in the REFSEL register field. It may also operate via
pin-selection of the desired input clock by selecting that mode in the
REFSEL register field. In that case, GPIOs must be used as Clock
Select inputs (CSELn). CSEL0 = 0 will select the CLK0 input and
CSEL0 = 1 will select the CLK1 input for PLL0. CSEL1 will perform
the same function for PLL1.
In addition, the crystal frequency may be passed directly to the output
dividers for Q[4:7] for use as a reference.
Inputs do not support transmission of spread-spectrum clocking
sources. Since this family is intended for high-performance
applications, it will assume input reference sources to have stabilities
of +100ppm or better, except where gapped clock inputs are used.
If the PLL is working in automatic mode, then each of the input
reference sources is assigned a priority of 1-2. At power-up or if the
currently selected input reference fails, the PLL will switch to the
highest priority input reference that is valid at that time (see Section,
“Input Clock Monitor” for details).
Automatic mode has two sub-options: revertive or non-revertive. In
revertive mode, the PLL will switch to a reference with a higher
priority setting whenever one becomes valid. In non-revertive mode
the PLL remains with the currently selected source as long as it
remains valid.
The clock input selection is based on the input clock priority set by
the Clock Input Priority control registers. It is recommended that all
input references for a PLL be given different priority settings in the
Clock Input Priority control registers for that PLL.
©2016 Integrated Device Technology, Inc.
6
Revision H, October 26, 2016

6 Page









8T49N283 pdf, datenblatt
8T49N283 Datasheet
I2C Master Mode
When operating in I2C mode, the 8T49N283 has the capability to
become a bus master on the I2C bus for the purposes of reading its
configuration from an external I2C EEPROM. Only a block read cycle
will be supported.
As an I2C bus master, the 8T49N283 will support the following
functions:
• 7-bit addressing mode
• Base address register for EEPROM
• Validation of the read block via CCITT-8 CRC check against value
stored in last byte (E0h) of EEPROM
• Support for 100kHz and 400kHz operation with speed negotiation.
If bit d0 is set at Byte address 05h in the EEPROM, this will shift
from 100kHz operation to 400kHz operation.
• Support for 1 or 2-byte addressing mode
• Master arbitration with programmable number of retries
• Fixed-period cycle response timer to prevent permanently hanging
the I2C bus.
• Read will abort with an alarm (BOOTFAIL) if any of the following
conditions occur: Slave NACK, Arbitration Fail, Collision during
Address Phase, CRC failure, Slave Response time-out
The 8T49N283 will not support the following functions:
• I2C General Call
• Slave clock stretching
• I2C Start Byte protocol
• EEPROM Chaining
• CBUS compatibility
• Responding to its own slave address when acting as a master
• Writing to external I2C devices including the external EEPROM
used for booting
Sequential Read (1byte offset address)
S Dev Addr + W A
Offset Addr
A Sr
Dev Addr + R
A
Data 0
A
Data 1
A
A Data n A P
Sequential Read (2byte offset address)
S
Dev Addr + W
A Offset Addr MSB A Offset Addr LSB A
Sr
Dev Addr + R
A
Data 0
A
Data 1
A
A Data n A P
from master to slave
S = start
from slave to master
Sr = repeated start
A = acknowledge
A = none acknowledge
P = stop
Figure 4. I2C Master Read Cycle Sequencing
I2C Boot-up Initialization Mode
If enabled (via the BOOT_EEP bit in the Startup register), once the
nRST input has been deasserted (high) and its internal power-up
reset sequence has completed, the device will contend for ownership
of the I2C bus to read its initial register settings from a memory
location on the I2C bus. The address of that memory location is kept
in non-volatile memory in the Startup register. During the boot-up
process, the device will not respond to serial control port accesses.
Once the initialization process is complete, the contents of any of the
device’s registers can be altered. It is the responsibility of the user to
make any desired adjustments in initial values directly in the serial
bus memory.
If a NACK is received to any of the read cycles performed by the
device during the initialization process, or if the CRC does not match
the one stored in address E0h of the EEPROM the process will be
aborted and any uninitialized registers will remain with their default
values. The BOOTFAIL bit (021Eh) in the Global Interrupt Status
register will also be set in this event.
If the BOOTFAIL bit is set, then both LOL[n] indicators will be set.
Contents of the EEPROM should be as shown in Table 5.
©2016 Integrated Device Technology, Inc.
12
Revision H, October 26, 2016

12 Page





SeitenGesamt 30 Seiten
PDF Download[ 8T49N283 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
8T49N281NG Octal Universal Frequency TranslatorIntegrated Device Technology
Integrated Device Technology
8T49N282NG Octal Universal Frequency TranslatorIntegrated Device Technology
Integrated Device Technology
8T49N283NG Octal Universal Frequency TranslatorIDT
IDT
8T49N285NG Octal Universal Frequency TranslatorIntegrated Device Technology
Integrated Device Technology
8T49N286NG Octal Universal Frequency TranslatorIntegrated Device Technology
Integrated Device Technology

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche