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Teilenummer | 813N252DI-02 |
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Beschreibung | Jitter Attenuator & FemtoClock NG Multiplier | |
Hersteller | IDT | |
Logo | ||
Gesamt 23 Seiten Jitter Attenuator & FemtoClock NG®
Multiplier
813N252DI-02
DATA SHEET
General Description
Features
The 813N252DI-02 device uses IDT's fourth generation
FemtoClock® NG technology for optimal high clock frequency and
low phase noise performance, combined with a low power
consumption and high power supply noise rejection. The
813N252DI-02 is a PLL based synchronous multiplier that is
optimized for PDH or SONET to Ethernet clock jitter attenuation and
frequency translation.
The813N252DI-02 is a fully integrated Phase Locked loop utilizing a
FemtoClock NG Digital VCXO that provides the low jitter, high
frequency SONET/PDH output clock that easily meets OC-48 jitter
requirements. This VCXO technology simplifies PLL design by
replacing the pullable crystal requirement of analog VCXOs with a
fixed 27MHz generator crystal. Jitter attenuation down to 10Hz is
provided by an external loop filter. Pre-divider and output divider
multiplication ratios are selected using device selection control pins.
The multiplication ratios are optimized to support most common
clock rates used in PDH, SONET and Ethernet applications. The
device requires the use of an external, inexpensive fundamental
mode 27MHz crystal. The device is packaged in a space-saving
32-VFQFN package and supports industrial temperature range.
Pin Assignment
LF1
32 31 30 29 28 27 26 25
1 24
• Fourth generation FemtoClock® NG technology
• Two LVPECL output pairs
• Each output supports independent frequency selection at 25MHz,
125MHz, 156.25MHz and 312.5MHz
• Two differential inputs support the following input types: LVPECL,
LVDS, LVHSTL, HCSL
• Accepts input frequencies from 8kHz to 155.52MHz including
8kHz, 1.544MHz, 2.048MHz, 19.44MHz, 25MHz, 77.76MHz,
125MHz and 155.52MHz
• Crystal interface optimized for a 27MHz, 10pF parallel resonant
crystal
• Attenuates the phase jitter of the input clock by using a low-cost
fundamental mode crystal
• Customized settings for jitter attenuation and reference tracking
using an external loop filter connection
• FemtoClock NG frequency multiplier provides low jitter, high
frequency output
• Absolute pull range: ±100ppm
• Power supply noise rejection (PSNR): -85dB (typical)
• FemtoClock NG VCXO frequency: 2500MHz
• RMS phase jitter @ 156.25MHz, using a 27MHz crystal
(12kHz – 20MHz): 0.6ps (typical)
• RMS phase jitter @ 125MHz, using a 27MHz crystal
(12kHz – 20MHz): 0.65ps (typical)
• 3.3V supply voltage
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
VEE
LF0 2
23 nQB
ISET 3
22 QB
VEE
CLK_SEL
4
5
813N252DI-02
21 VCCO
20 nQA
VCC
RESERVED
VEE
6
7
8
9
19
18
17
10 11 12 13 14 15 16
QA
VEE
ODASEL_0
32-pin, 5mm x 5mm VFQFN Package
REVISION 1 08/14/15
1
©2015 INTEGRATED DEVICE TECHNOLOGY, INC.
813N252DI-02 DATA SHEET
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, VCC
Inputs, VI
XTAL_IN
Other Inputs
Outputs, IO
Continuous Current
Surge Current
Package Thermal Impedance, JA
Storage Temperature, TSTG
Rating
3.63V
0V to 2V
-0.5V to VCC+ 0.5V
50mA
100mA
33.1C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. LVPECL Power Supply DC Characteristics, VCC = VCCO = VCCX = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VCC
VCCA
VCCO
VCCX
IEE
ICCA
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Crystal Supply Voltage
Power Supply Current
Analog Supply Current
3.135
VCC – 0.30
3.135
3.135
3.3
3.3
3.3
3.3
253
3.465
VCC
3.465
3.465
321
30
V
V
V
V
mA
mA
Table 4B. LVCMOS/LVTTL DC Characteristics, VCC = VCCO = VCCX = 3.3V ± 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum Typical
VIH Input High Voltage
VIL Input Low Voltage
CLK_SEL,
IIH
Input
High Current
ODASEL_[1:0],
ODBSEL_[1:0]
PDSEL_[2:0]
CLK_SEL,
IIL
Input
Low Current
ODASEL_[1:0],
ODBSEL_[1:0]
PDSEL_[2:0]
VCC = VIN = 3.465V
VCC = VIN = 3.465V
VCC = 3.465V, VIN = 0V
VCC = 3.465, VIN = 0V
2
-0.3
-10
-150
Maximum
VCC + 0.3
0.8
150
10
Units
V
V
µA
µA
µA
µA
REVISION 1 08/14/15
6 JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER
6 Page 813N252DI-02 DATA SHEET
3.3V Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, HCSL and other
differential signals. Both differential inputs must meet the VPP and
VCMR input requirements. Figures 2A to 2E show interface examples
for the CLK /nCLK input driven by the most common driver types. The
input interfaces suggested here are examples only. Please consult
with the vendor of the driver component to confirm the driver
termination requirements. For example, in Figure 2A, the input
termination applies for IDT open emitter LVHSTL drivers. If you are
using an LVHSTL driver from another vendor, use their termination
recommendation.
1.8V
Zo = 50Ω
Zo = 50Ω
LVHSTL
IDT
LVHSTL Driver
3.3V
CLK
R1 R2
50Ω 50Ω
nCLK
Differential
Input
Figure 2A. CLK/nCLK Input Driven by an
IDT Open Emitter LVHSTL Driver
Figure 2B. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
Figure 2C. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
Figure 2D. CLK/nCLK Input Driven by a
3.3V LVDS Driver
3.3V
3.3V
*R3 33Ω
Zo = 50Ω
Zo = 50Ω
HCSL
*R4 33Ω
*Optional – R3 and R4 can be 0Ω
R1
50Ω
CLK
nCLK
R2
50Ω
Differential
Input
Figure 2E. CLK/nCLK Input Driven by an HCSL Driver
REVISION 1 08/14/15
12 JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER
12 Page | ||
Seiten | Gesamt 23 Seiten | |
PDF Download | [ 813N252DI-02 Schematic.PDF ] |
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