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SJ7500P Schematic ( PDF Datasheet ) - AUK

Teilenummer SJ7500P
Beschreibung Pulse Width Modulation
Hersteller AUK
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Gesamt 11 Seiten
SJ7500P Datasheet, Funktion
Semiconductor
SJ7500/P
Pulse Width Modulation
Description
The SJ7500 is a monolithic integrated circuit which includes all the necessary building
blocks for the design of pulse width modulate(PWM) switching power supplies, including
push-pull, bridge and series configuration. The precision of voltage reference is improved
up to ±1% through trimming and this provides a better output voltage regulation. The
device can operate at switching frequencies between 1KHz and 300KHz and output voltage
up to 23V. The SJ7500 is specified over an operating temperature range of -25~+85.
Features
Package Type
Internal Regulator Provides a Stable 5V
Reference Supply Trimmed to ±1% Accuracy
Uncommitted output transistors capable
of 200mA source or sink
Internal protection from double pulsing of
out-puts with narrow pulse widths or with
supply voltages below specified limits
Easily synchronized to other circuits
Dead time control comparator
Output control selects single-ended or
push-pull operation
Operating temperature range : -25~ +85
Halogen-Free Package is Available
High Level ESD Protection : 400V(MM), 4KV(HBM)
Application
SOP-16
DIP-16
Charger
SMPS
Back Light Inverter
Ordering Information
PKG Type
SJ7500
SJ7500P
Device Name
SOP-16
DIP-16
Marking
SJ7500
SJ7500P
KSD-I7D001-000
1






SJ7500P Datasheet, Funktion
SJ7500/P
Test Circuit
Fig.1 Error Amplifier Test Circuit
Fig.2 Current Limit sense Amplifier Test Circuit
+
VIN
-
V REF
1+
ERROR
2 -AMP
16 +
ERROR
-AMP
15
V3
Fig. 3 Common-Emitter Configuration
Test circuit and Waveform
Each output
Trans is tor
15V DC
68
C Vc
15p F
E
90%
10%
Tr
90%
10%
Tf
V REF
+
V IN
-
1+
ERROR
2 -AMP
16 +
ERROR
-AMP
15
V3
Fig. 5 Dead-Time and Feedback Control
Test Circuit
Vcc=15V
TEST
Inputs
12
4 DEAD Vcc
3
TIME
FEED BACK
150
2W
8
C1
E1 9
12K
6
5
RT
CT
0.01uF
1
2
(+)
(-)
16 (+)
15 (-)
13 OUTPUT
C2
E2
11
10
REF 14
50K
CONTROL
OUT
7 GND
150
2W
OUTPUT1
OUTPUT2
Fig. 4 Emitter-Follower Configuration Test circuit and waveform Voltage waveform
Each output
Tr ans i s t or
15V DC
C
VE
68 15pF
90%
10%
GND
Tr
90%
10%
Tf
KSD-I7D001-000
6

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