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PDF AD664 Data sheet ( Hoja de datos )

Número de pieza AD664
Descripción Monolithic 12-Bit Quad DAC
Fabricantes Analog Devices 
Logotipo Analog Devices Logotipo



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a
Monolithic
12-Bit Quad DAC
AD664
FEATURES
Four Complete Voltage Output DACs
Data Register Readback Feature
“Reset to Zero” Override
Multiplying Operation
Double-Buffered Latches
Surface Mount and DIP Packages
MIL-STD-883 Compliant Versions Available
APPLICATIONS
Automatic Test Equipment
Robotics
Process Control
Disk Drives
Instrumentation
Avionics
PRODUCT DESCRIPTION
The AD664 is four complete 12-bit, voltage-output DACs on
one monolithic IC chip. Each DAC has a double-buffered input
latch structure and a data readback function. All DAC read and
write operations occur through a single microprocessor-compatible
I/O port.
The I/O port accommodates 4-, 8- or 12-bit parallel words al-
lowing simple interfacing with a wide variety of microprocessors.
A reset to zero control pin is provided to allow a user to simulta-
neously reset all DAC outputs to zero, regardless of the contents
of the input latch. Any one or all of the DACs may be placed in
a transparent mode allowing immediate response by the outputs
to the input data.
The analog portion of the AD664 consists of four DAC cells,
four output amplifiers, a control amplifier and switches. Each
DAC cell is an inverting R-2R type. The output current from
each DAC is switched to the on-board application resistors and
output amplifier. The output range of each DAC cell is pro-
grammed through the digital I/O port and may be set to unipo-
lar or bipolar range, with a gain of one or two times the reference
voltage. All DACs are operated from a single external reference.
The functional completeness of the AD664 results from the
combination of Analog Devices’ BiMOS II process, laser-trimmed
thin-film resistors and double-level metal interconnects.
PRODUCT HIGHLIGHTS
1. The AD664 provides four voltage-output DACs on one chip
offering the highest density 12-bit D/A function available.
2. The output range of each DAC is fully and independently
programmable.
3. Readback capability allows verification of contents of the in-
ternal data registers.
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
PIN CONFIGURATIONS
44-Pin Package
28-Pin DIP Package
4. The asynchronous RESET control returns all D/A outputs
to zero volts.
5. DAC-to-DAC matching performance is specified and tested.
6. Linearity error is specified to be 1/2 LSB at room tempera-
ture and 3/4 LSB maximum for the K, B and T grades.
7. DAC performance is guaranteed to be monotonic over the
full operating temperature range.
8. Readback buffers have tristate outputs.
9. Multiplying-mode operation allows use with fixed or vari-
able, positive or negative external references.
10. The AD664 is available in versions compliant with MIL-
STD-883. Refer to the Analog Devices Military Products
Databook or current AD664/883B data sheet for detailed
specifications.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/461-3113

1 page




AD664 pdf
AD664
Figure 1a. 44-Pin Block Diagram
FUNCTIONAL DESCRIPTION
The AD664 combines four complete 12-bit voltage output D/A
converters with a fast, flexible digital input/output port on one
monolithic chip. It is available in two forms, a 44-pin version
shown in Figure 1a and a 28-pin version shown in Figure 1b.
tions. This register may also be read back to check its contents.
A RESET-TO-ZERO feature allows all DACs to be reset to 0
volts out by strobing a single pin.
44-Pin Versions
Each DAC offers flexibility, accuracy and good dynamic perfor-
mance. The R-2R structure is fabricated from thin-film resistors
which are laser-trimmed to achieve 1/2 LSB linearity and guar-
anteed monotonicity. The output amplifier combines the best
features of the bipolar and MOS devices to achieve good dy-
namic performance and low offset. Settling time is under 10 µs
and each output can drive a 5 mA, 500 pF load. Short-circuit
protection allows indefinite shorts to VLL, VCC, VEE and GND.
The output and span resistor pins are available separately. This
feature allows a user to insert current-boosting elements to in-
crease the drive capability of the system, as well as to overcome
parasitics.
Digital circuitry is implemented in CMOS logic. The fast, low
power, digital interface allows the AD664 to be interfaced with
most microprocessors. Through this interface, the wide variety
of features on each chip may be accessed. For example, the in-
put data for each DAC is programmed by way of 4-, 8-, 12- or
16-bit words. The double-buffered input structure of this latch
allows all four DACs to be updated simultaneously. A readback
feature allows the internal registers to be read back through the
same digital port, as either 4-, 8- or 12-bit words. When dis-
abled, the readback drivers are placed in a high impedance
(tristate) mode. A TRANSPARENT mode allows the input data
to pass straight through both ranks of input registers and appear
at the DAC with a minimum of delay. One D/A may be placed
in the transparent mode at a time, or all four may be made
transparent at once. The MODE SELECT feature allows the
output range and mode of the DACs to be selected via the data
bus inputs. An internal mode select register stores the selec-
Figure 1b. 28-Pin Block Diagram
28-Pin Versions
The 28-pin versions are dedicated versions of the 44-pin
AD664. Each offers a reduced set of features from those offered
in the 44-pin version. This accommodates the reduced number
of package pins available. Data is written and read with 12-bit
words only. Output range and mode select functions are also
not available in 28-pin versions. As an alternative, users specify
either the UNI (unipolar, 0 to VREF) models or the BIP (bipolar,
–VREF to VREF) models depending on the application require-
ments. Finally, the transparent mode is not available on the
28-pin versions.
–4– REV. D

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AD664 arduino
AD664
occupies the topmost eight bits of the input word. The last four
bits of the input word are “don’t cares.”
Figure 15 shows the format of the MODE SELECT word. The
first four bits determine the gain range of the DAC. When set to
be a gain of 1, the output of the DAC spans a voltage of 1 times
the reference. When set to a gain of 2, the output of the DAC
spans a voltage of 2 times the reference.
The next four bits determine the mode of the DAC. When set to
UNIPOLAR, the output goes from 0 to REF or 0 to 2 REF.
When the BIPOLAR mode is selected, the output goes from
–REF/2 to REF/2 or –REF to REF.
Preloading the Mode Select Register
Mode data can be written into the first rank of the mode select
latch without changing the modes currently being used. This
feature is useful when a user wants to preload new mode infor-
mation in anticipation of strobing that in at a future time. Fig-
ure 17 illustrates the correct sequence and timing of control
signals to accomplish this task.
This allows the user to “preload” the data to a DAC and strobe
it into the output latch at some future time. The user could do
this by reproducing the sequence of signals illustrated in Figures
17c and 17d.
Figure 15. Mode Select Word Format
Load and Update Mode of One DAC
In this next example, the object is to load new mode informa-
tion for one of the DACs into the first rank of latches and then
immediately update the second rank. This is done by putting the
new mode information (8-bit word length) onto the databus.
Then MS and LS are pulled low. Following that, CS is pulled
low. This loads the mode information into the first rank of
latches. LS is then brought high. This action updates the second
rank of latches (and, therefore, the DAC outputs). The load
cycle ends when CS is brought high.
In reality, this load cycle really updates the modes of all the
DACs, but the effect is to only change the modes of those
DACs whose mode select information has actually changed.
Figure 17a. Preload Mode Select Register
Figure 17b. Preload Mode Select Register Timing
DATA
1
INPUT/OUTPUT
BITS
0
__A_DD__R_ES_S__ 1
QS0,QS1,QS2
DS0,DS1
0
__
MS
__
CS
t MS
t MH
tW
Figure 17c. Update Second Rank of Mode Select Latch
Figure 16a. Load and Update Mode of One DAC
SYMBOL
25؇C
MIN (ns)
TMIN to TMAX
MIN (ns)
tMS 0
tLS* 0
tDS 0
tLW 60
tCH 70
tDH 0
tMH 0
0
0
0
70
80
0
0
*FOR tLS > 0, THE WIDTH OF LS MUST BE
INCREASED BY THE SAME AMOUNT THAT
tLS IS GREATER THAN 0 ns.
Figure 16b. Load and Update Mode of One DAC Timing
SYMBOL
tMS
tMH
tW
25؇C
MIN (ns)
0
0
80
TMIN to TMAX
MIN (ns)
0
0
100
Figure 17d. Update Second Rank of Mode Select Latch
Timing
Transparent Operation (44-Pin Versions)
Transparent operation allows data from the inputs of the
AD664 to be transferred into the DAC registers without the
intervening step of being latched into the first rank of latches.
Two modes of transparent operation exist, the “partially trans-
parent” mode and a “fully transparent” mode. In the “partially
transparent” mode, one of the DACs is transparent while the
remaining three continue to use the data latched into their
respective input registers. Both modes require a 12-bit wide
input word!
–10–
REV. D

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