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ADV7310 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADV7310
Beschreibung Video Encoder
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
ADV7310 Datasheet, Funktion
Multiformat 216 MHz
Video Encoder with Six NSV12-Bit DACs
ADV7310/ADV7311
FEATURES
High Definition Input Formats
8-/10-, 16-/20-, 24-/30-Bit (4:2:2, 4:4:4) Parallel YCrCb
Compliant with:
SMPTE 293M (525p)
BTA T-1004 EDTV2 (525p)
ITU-R BT.1358 (625p/525p)
ITU-R BT.1362 (625p/525p)
SMPTE 274M (1080i) at 30 Hz and 25 Hz
SMPTE 296M (720p)
RGB in 3؋10-Bit 4:4:4 Input Format
HDTV RGB Supported:
RGB, RGBHV
Other High Definition Formats Using Async
Timing Mode
High Definition Output Formats
YPrPb Progressive Scan (EIA-770.1, EIA-770.2)
YPrPb HDTV (EIA 770.3)
RGB, RGBHV
CGMS-A (720p/1080i)
Macrovision Rev 1.1 (525p/625p)*
CGMS-A (525p)
Standard Definition Input Formats
CCIR-656 4:2:2 8-/10-/16-/20-Bit Parallel Input
Standard Definition Output Formats
Composite NTSC M/N
Composite PAL M/N/B/D/G/H/I, PAL-60
SMPTE 170M NTSC Compatible Composite Video
ITU-R BT.470 PAL Compatible Composite Video
S-Video (Y/C)
EuroScart RGB
Component YPrPb (Betacam, MII, SMPTE/EBU N10)
Macrovision Rev 7.1.L1*
CGMS/WSS
Closed Captioning
GENERAL FEATURES
Simultaneous SD and HD Inputs and Outputs
Oversampling up to 216 MHz
Programmable DAC Gain Control
Sync Outputs in All Modes
On-Board Voltage Reference
Purchase of licensed I2C components of Analog Devices or one of its
sublicensed Associated Companies conveys a license for the purchaser under
the Philips I2C Patent Rights to use these components in an I2C system,
provided that the system conforms to the I2C Standard Specification as
defined by Philips.
*ADV7310 Only
Six 12-Bit NSV Precision Video DACs
2-Wire Serial I2C® Interface
Dual I/O Supply 2.5 V/3.3 V Operation
Analog and Digital Supply 2.5 V
On-Board PLL
64-Lead LQFP Package
Lead (Pb) Free Product
APPLICATIONS
High End DVD
High End PS DVD Recorders/Players
SD/Prog Scan/HDTV Display Devices
SD/HDTV Set Top Boxes
Professional Video Systems
SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM
Y9–Y0
C9–C0
S9–S0
HSYNC
VSYNC
BLANK
CLKIN_A
CLKIN_B
STANDARD DEFINITION
CONTROL BLOCK
COLOR CONTROL
BRIGHTNESS
DNR
GAMMA
PROGRAMMABLE FILTERS
SD TEST PATTERN
D
E
M
U
X
TIMING
GENERATOR
PROGRAMMABLE
RGB MATRIX
HIGH DEFINITION
CONTROL BLOCK
HD TEST PATTERN
COLOR CONTROL
ADAPTIVE FILTER CTRL
SHARPNESS FILTER
PLL
ADV7310/
ADV7311
12-BIT
DAC
O 12-BIT
V DAC
E
R
S
A
12-BIT
DAC
M
P 12-BIT
L DAC
I
N 12-BIT
G DAC
12-BIT
DAC
I2C
INTERFACE
GENERAL DESCRIPTION
The ADV®7310/ADV7311 is a high speed, digital-to-analog
encoder on a single monolithic chip. It includes six high speed
NSV video D/A converters with TTL compatible inputs.
The ADV7310/ADV7311 has separate 8-/10-/16-/20-bit input
ports that accept data in high definition and/or standard definition
video format. For all standards, external horizontal, vertical,
and blanking signals or EAV/SAV timing codes control the
insertion of appropriate synchronization signals into the digi-
tal data stream and therefore the output signal.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.






ADV7310 Datasheet, Funktion
ADV7310/ADV7311
TIMING SPECIFICATIONS (VAA = 2.375 V–2.625 V, VDD = 2.375 V–2.625 V; VDD_IO = 2.375 V–3.6 V, VREF = 1.235 V, RSET = 3040 ,
RLOAD = 300 . All specifications TMIN to TMAX (0؇C to 70؇C), unless otherwise noted.)
Parameter
Min Typ Max Unit
Test Conditions
MPU PORT1
SCLOCK Frequency
SCLOCK High Pulsewidth, t1
SCLOCK Low Pulsewidth, t2
Hold Time (Start Condition), t3
Setup Time (Start Condition), t4
Data Setup Time, t5
SDATA, SCLOCK Rise Time, t6
SDATA, SCLOCK Fall Time, t7
Setup Time (Stop Condition), t8
RESET Low Time
0
0.6
1.3
0.6
0.6
100
0.6
100
400 kHz
µs
µs
µs
µs
ns
300 ns
300 ns
µs
ns
First clock generated after this period
relevant for repeated start condition
ANALOG OUTPUTS
Analog Output Delay2
Output Skew
7 ns
1 ns
CLOCK CONTROL AND PIXEL PORT3
fCLK
fCLK
Clock High Time, t9
Clock Low Time, t10
Data Setup Time, t111
Data Hold Time, t121
SD Output Access Time, t13
SD Output Hold Time, t14
HD Output Access Time, t13
HD Output Hold Time, t14
PIPELINE DELAY4
40
40
2.0
2.0
5.0
5.0
81
63
76
35
41
36
27 MHz
Progressive scan mode
MHz
HDTV mode/async mode
% of one clk cycle
% of one clk cycle
ns
ns
15 ns
ns
14 ns
ns
clk cycles
clk cycles
clk cycles
clk cycles
clk cycles
SD [2ϫ, 16ϫ]
SD component mode [16ϫ]
PS [1ϫ]
PS [8ϫ]
HD[2ϫ, 1ϫ]
NOTES
1Guaranteed by characterization.
2Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of DAC output full-scale transition.
3Data: C[9:0]; Y[9:0], S[9:0]
Control: P_HSYNC, P_VSYNC, P_BLANK, S_HSYNC, S_VSYNC, S_BLANK.
4SD, PS = 27 MHz, HD = 74.25 MHz.
Specifications subject to change without notice.
–6– REV. A

6 Page









ADV7310 pdf, datenblatt
ADV7310/ADV7311
CLKIN_A
CONTROL
INPUTS
S_HSYNC,
S_VSYNC,
S_BLANK
S9–S0/Y9–Y0*
t9 t10
Y0
t12
Y1
Y2
IN SLAVE MODE
Y3
C9–C0
CONTROL
OUTPUTS
Cb0
t11
Cr0
Cb2
t13
t14
Cr2
*SELECTED BY ADDRESS 0x01 BIT 7
Figure 12. 20-/16-Bit SD Only Pixel Input Mode [Input Mode 000]
IN MASTER/SLAVE MODE
P_HSYNC
P_VSYNC
P_BLANK
a
Y9–Y0
Y0 Y1 Y2 Y3
C9–C0
Cb0 Cr0 Cr1 Cb1
b
a = 16 CLKCYCLES FOR 525p
a = 12 CLKCYCLES FOR 626p
a = 44 CLKCYCLES FOR 1080i @ 30Hz, 25Hz
a = 70 CLKCYCLES FOR 720p
AS RECOMMENDED BY STANDARD
b(MIN) = 122 CLKCYCLES FOR 525p
b(MIN) = 132 CLKCYCLES FOR 625p
b(MIN) = 236 CLKCYCLES FOR 1080i @ 30Hz, 25Hz
b(MIN) = 300 CLKCYCLES FOR 720p
Figure 13. HD 4:2:2 Input Timing Diagram
–12–
REV. A

12 Page





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