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ST7066 Datasheet Detailansicht - Sitronix

Teilenummer ST7066 Schematic
Beschreibung Dot Matrix LCD Controller/Driver
Hersteller Sitronix
Logo Sitronix Logo 
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ST7066 Datenblatt PDF

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ST7066 Datasheet, Funktion
ST7066
FUNCTION DESCRIPTION
System Interface
This chip has all two kinds of interface type with MPU : 4-bit bus and 8-bit bus. 4-bit bus or 8-bit bus is selected by DL
bit in the instruction register.
During read or write operation, two 8-bit registers are used. One is data register (DR), the other is instruction
register(IR).
The data register(DR) is used as temporary data storage place for being written into or read from DDRAM/CGRAM,
target RAM is selected by RAM address setting instruction. Each internal operation, reading from or writing into
RAM, is done automatically. So to speak, after MPU reads DR data, the data in the next DDRAM/CGRAM address is
transferred into DR automatically. Also after MPU writes data to DR, the data in DR is transferred into
DDRAM/CGRAM automatically.
The Instruction register(IR) is used only to store instruction code transferred from MPU. MPU cannot use it to read
instruction data.
To select register, use RS input pin in 4-bit/8-bit bus mode.
Table 1. Various kinds of operations according to RS and R/W bits.
RS RW
Operation
L L Instruction Write operation (MPU writes Instruction code
into IR)
L H Read Busy Flag(DB7) and address counter (DB0 ~ DB6)
H L Data Write operation (MPU writes data into DR)
H H Data Read operation (MPU reads data from DR)
Busy Flag (BF)
When BF = "High”, it indicates that the internal operation is being processed. So during this time the next instruction
cannot be accepted. BF can be read, when RS = Low and R/W = High (Read Instruction Operation), through DB7
port. Before executing the next instruction, be sure that BF is not High.
Address Counter (AC)
Address Counter(AC) stores DDRAM/CGRAM address, transferred from IR.
After writing into (reading from) DDRAM/CGRAM, AC is automatically increased (decreased) by 1.
When RS = "Low" and R/W = "High", AC can be read through DB0 ~ DB6 ports.
V1.2
6 2000/6/13

6 Page

ST7066 pdf, datenblatt
ST7066
Character Code
(DDRAM Data)
CGRAM
Address
Character Patterns
(CGRAM Data)
b7 b6 b5 b4 b3 b3 b1 b0 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0
000
000
11111
000
001
00100
000
010
00100
0000 - 000000011 - - - 00100
000
100
00100
000
101
00100
000
110
00100
000
111
00000
001
000
11110
001
001
10001
001
010
10001
0000 - 001000011 - - - 11110
001
100
10100
001
101
10010
001
110
10001
001
111
00000
Table 5 Relationship between CGRAM Addresses, Character Codes (DDRAM) and Character patterns (CGRAM Data)
Notes:
1. Character code bits 0 to 2 correspond to CGRAM address bits 3 to 5 (3 bits: 8 types).
2. CGRAM address bits 0 to 2 designate the character pattern line position. The 8th line is the
cursor position and its display is formed by a logical OR with the cursor. Maintain the 8th line data, corresponding
to the cursor display position, at 0 as the cursor display. If the 8th line data is 1, 1 bits will light up the 8th line
regardless of the cursor presence.
3. Character pattern row positions correspond to CGRAM data bits 0 to 4 (bit 4 being at the left).
4. As shown Table 5, CGRAM character patterns are selected when character code bits 4 to 7 are
all 0. However, since character code bit 3 has no effect, the R display example above can be selected by either
character code 00H or 08H.
5. 1 for CGRAM data corresponds to display selection and 0 to non-selection.
“-“: Indicates no effect.
V1.2
12 2000/6/13

12 Page





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