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PDF G65SC22 Data sheet ( Hoja de datos )
| Número de pieza | G65SC22 | |
| Descripción | CMOS VERSATILE INTERFACE ADAPTER | |
| Fabricantes | California Micro Devices Corp | |
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A CALIFORNIA MICRO DEVICES
G65SC22
CMOS VERSATILE INTERFACE ADAPTER WITH INTERVAL
TIM E R /C O U N TER S
Features
• CM OS process technology for low power consumption
• Fully com patible with NMOS 6522 devices
• Low power consumption allows battery-powered
operation (2m A at 1MHz)
• Two 8-bit, bidirectional peripheral I/O ports
• Two powerful 16-bit program mable timer/counters
• Serial bidirectional peripheral I/O port
• Enhanced "handshake" feature
• Latched input/output registers on both I/O ports
• Programmable data direction registers
• Four operating frequencies — 1, 2, 3,and 4 MHz
• TTL com patible I/O peripheral lines
• Single + 5 volts power supply
• Available in 40-pin DIP or 44-pin PLCC package
Contact factory for complete data sheet.
Product Description
The CM D G 65SC22 Versatile Interface Adapter (VIA) is a flexible I/O device for use with the CM D G 6 5 S C X X X series 8-bit
m icroprocessor family. The G 65SC22 includes functions for program m ed control of up to tw o peripheral devices (Ports
A and B). Two program controlled 8-bit bidirectional peripheral I/O ports allow direct interfacing between the m icro
processor and selected peripheral units. Each port has input data latching capacity. Two program m able data direction
registers (A and B) allow selection of data direction (input or output) on a individual line basis. Also provided are two
program m able 16-bit interval timer/counters with latches. Tim er 1 may be operated in a one-shot interrupt mode with
interrupts on each count-to-zero, or in a free-run mode with a continuous series of evenly spaced interrupts. Tim er 2
functions as both an interval and pulse counter. Serial data transfers are provided by a serial-to-parallel/parallel-to-serial
shift register. Application versatility is further increased by various control registers, including — an interrupt flag
register, an interrupt enable register and two function control registers.
Block Diagram
© 1 9 8 7 , 1 9 9 6 C M D C o rp . A ll r ig h ts reserved.__________________________________________________________________________________________________________________________________
10 /9 7 Rev. 2
2 1 5 Topaz Street, M ilpitas, C alifo rnia 9 5 0 3 5 A Tel: (4 0 8 )2 6 3 -3 2 1 4 A. Fax: (4 0 8 )2 6 3 -7 8 4 6
1 page | ||
| Páginas | Total 2 Páginas | |
| PDF Descargar | [ Datasheet G65SC22.PDF ] | |
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