PDF SN74LS221 Data sheet ( Hoja de datos )

Número de pieza	SN74LS221
Descripción	DUAL MONOSTABLE MULTIVIBRATORS
Fabricantes	Motorola Semiconductors
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No Preview Available ! DUAL MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER INPUTS Each multivibrator of the LS221 features a negative-transition-triggered input and a positive-transition-triggered input either of which can be used as an inhibit input. Pulse triggering occurs at a voltage level and is not related to the transition time of the input pulse. Schmitt-trigger input circuitry for B input allows jitter-free triggering for inputs as slow as 1 volt/ second, providing the circuit with excellent noise immunity. A high immunity to VCC noise is also provided by internal latching circuitry. Once triggered, the outputs are independent of further transitions of the inputs and are a function of the timing components. The output pulses can be terminated by the overriding clear. Input pulse width may be of any duration relative to the output pulse width. Output pulse width may be varied from 35 nanoseconds to a maximum of 70 s by choosing appropriate timing components. With Rext = 2.0 kΩ and Cext = 0, a typical output pulse of 30 nanoseconds is achieved. Output rise and fall times are independent of pulse length. Pulse width stability is achieved through internal compensation and is virtually independent of VCC and temperature. In most applications, pulse stability will only be limited by the accuracy of external timing components. Jitter-free operation is maintained over the full temperature and VCC ranges for greater than six decades of timing capacitance (10 pF to 10 µF), and greater than one decade of timing resistance (2.0 to 70 kΩ for the SN54LS221, and 2.0 to 100 kΩ for the SN74LS221). Pulse width is defined by the relationship: tw(out) = CextRext ln 2.0 ≈ 0.7 Cext Rext; where tW is in ns if Cext is in pF and Rext is in kΩ . If pulse cutoff is not critical, capacitance up to 1000 µF and resistance as low as 1.4 kΩ may be used. The range of jitter-free pulse widths is extended if VCC is 5.0 V and 25°C temperature. • SN54LS221 and SN74LS221 is a Dual Highly Stable One-Shot • Overriding Clear Terminates Output Pulse • Pin Out is Identical to SN54/ 74LS123 SN54/74LS221 DUAL MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER INPUTS LOW POWER SCHOTTKY 16 1 J SUFFIX CERAMIC CASE 620-09 16 1 N SUFFIX PLASTIC CASE 648-08 16 1 D SUFFIX SOIC CASE 751B-03 ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC (TOP VIEW) 1 Rext/ 1 2 VCC Cext Cext 1Q 2Q CLR 2B 16 15 14 13 12 11 10 Q Q CLR CLR Q Q 2A 9 1 2 3 4 56 78 1A 1B 1 1Q 2Q 2 2 Rext/ GND CLR Cext Cext positive logic: Low input to clear resets Q low and positive logic: Q high regardless of dc levels at A positive logic: or B inputs. + Cext FUNCTION TABLE (EACH MONOSTABLE) INPUTS OUTPUTS CLEAR A B Q Q L XX L H VCC X HX L H X XL L H Rext H L ° H ±H ° L H R/C See operational notes — Pulse Trigger Modes TYPE SN54LS221 SN74LS221 TYPICAL POWER DISSIPATION 23 mW 23 mW MAXIMUM OUTPUT PULSE LENGTH 49 s 70 s FAST AND LS TTL DATA 5-380 1 page SN54 / 74LS221 AC WAVEFORMS B INPUT tW(in) ≥60 ns 1.3 V CLEAR Q OUTPUT tPLH tPHL Q OUTPUT tPHL tPLH A INPUT IS LOW. TRIGGER FROM B, THEN CLEAR — CONDITION 1 B INPUT CLEAR ≥ 60 ns 1.3 V Q OUTPUT A INPUT IS LOW. TRIGGER FROM B, THEN CLEAR — CONDITION 2 B INPUT CLEAR ≥ 50 ns ≥ 0 ts TRIGGERED Q OUTPUT NOT TRIGGERED tW(out) A INPUT IS LOW. CLEAR OVERRIDING B, THEN TRIGGER FROM B B INPUT CLEAR ≥ 50 ns ≥ 50 ns 1.3 V Q OUTPUT A INPUT IS LOW. TRIGGERING FROM POSITIVE TRANSITION OF CLEAR 3V 0V 3V 0V VOH VOL VOH VOL 3V 0V 3V 0V VOH VOL 3V 0V 3V 0V VOH VOL 3V 0V 3V 0V VOH VOL Figure 1 FAST AND LS TTL DATA 5-384 5 Page

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