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PDF IR3523 Data sheet ( Hoja de datos )
| Número de pieza | IR3523 | |
| Descripción | DUAL OUTPUT CONTROL IC | |
| Fabricantes | International Rectifier | |
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IR3523
DATASHEET
XPHASE3TM DUAL OUTPUT CONTROL IC
DESCRIPTION
The IR3523 Control IC provides a full featured and flexible way to implement a complete dual output DDR &
CPU VTT multiphase power solution for Intel VR11.1 motherboards. Each output interfaces with any number of
xPHASE3TM Phase ICs each driving and monitoring a single phase. Output 1 includes a 3 bit VR11.x VID, 1.1V
boot voltage and droop to implement the CPU VTT rail which is typically 1 phase. Output 2 includes a 3 bit VID for
margining and supports any number of phases and DDR DIMM modules. The xPHASE3TM architecture results in a
power supply that is smaller, less expensive, and easier to design while providing higher efficiency than
conventional approaches.
INDEPENDENT FEATURES FOR BOTH OUTPUT 1 & 2
• Enable Input
• Power Good (PG) Output
• 0.5% overall system set point accuracy
• Programmable Softstart
• High speed error amplifier with wide bandwidth of 30MHz and fast slew rate of 12V/us
• Remote sense amplifier provides differential sensing and requires less than 50uA bias current
• Programmable over current threshold triggers constant converter output current limit during start-up and
hiccup protection during normal operation
• Over voltage condition communicated to phase ICs by IIN (ISHARE) and system by ROSC/OVP pins
• Detection and protection of open remote sense lines
OUTPUT 1 ADDITIONAL FEATURES
• 3 bit Intel VR11.x VID (VID4, VID3, VID2)
• Programmable VID offset
• 1.1 V Boot Voltage
• Programmable output impedance
• Programmable VID-on-the-Fly Slew Rate
OUTPUT 2 ADDITIONAL FEATURES
• 3 bit VID provides 1.5 V with ±150mV margining
• Programmable VID-on-the-Fly Slew Rate
FEATURES SHARED BY BOTH OUTPUTS 1 & 2
• Programmable per phase switching frequency of 250kHz to 1.5MHz
• Daisy-chain digital phase timing provides accurate phase interleaving without external components
• Gate Drive and IC bias linear regulator control with programmable output voltage and UVLO
• Over voltage signal to system with over voltage detection during powerup and normal operation
ORDERING INFORMATION
Device
IR3523MTRPBF
* IR3523MPBF
* Samples only
Package
40 Lead MLPQ (6 x 6 mm body)
40 Lead MLPQ (6 x 6 mm body)
Order Quantity
3000 per reel
100 piece strips
Page 1 of 37
June 20, 2008
1 page  
IR3523
RECOMMENDED OPERATING CONDITIONS FOR RELIABLE OPERATION WITH MARGIN
4.75V ≤ VCCL ≤ 7.5V, -0.3V ≤ VOSEN-x ≤ 0.3V, 0 oC ≤ TJ ≤ 100 oC, 7.75 kΩ ≤ ROSC ≤ 50 kΩ, CSS/DELx = 0.1uF
ELECTRICAL CHARACTERISTICS
The electrical characteristics involve the spread of values guaranteed within the recommended operating
conditions (unless otherwise specified). Typical values represent the median values, which are related to 25°C.
PARAMETER
System Set Point Accuracy
Deviation from Table 1 for Output
1 and deviation from Table 2 for
Output 2 per test circuit in Figure
4a and 4b, respectively
VIDx Interface
Input Thresholds
Pull-Down Resistance
Oscillator
PHSOUT Frequency
TEST CONDITION
Output 2 and Output 1
Output 2 at 1.8V (only)
Increasing
Decreasing (VID2_0 and VID2_1 Only)
Hysteresis (VID2_0 and VID2_1 Only)
ROSC Voltage
CLKOUT High Voltage
CLKOUT Low Voltage
I(CLKOUT)= -10 mA, measure V(VCCL) –
V(CLKOUT).
I(CLKOUT)= 10 mA
PHSOUT High Voltage
PHSOUT Low Voltage
I(PHSOUT)= -1 mA, measure V(VCCL) –
V(PHSOUT)
I(PHSOUT)= 1 mA
PHSIN Threshold Voltage
Compare to V(VCCL)
VDRP1 Buffer Amplifiers
Input Offset Voltage
V(VDRP) – V(IIN), 0.5V ≤ V(IIN) ≤ 3.3V
Source Current
0.5V ≤ V(IIN1) ≤ 3.3V
Sink Current
0.5V ≤ V(IIN1) ≤ 3.3V
Unity Gain Bandwidth
Note 1
Slew Rate
Note 1
IIN Bias Current
Remote Sense Differential Amplifiers
Unity Gain Bandwidth
Note 1
Input Offset Voltage
Source Current
0.5V≤ V(VOSENx+) - V(VOSENx-) ≤ 1.6V,
Note 2
0.5V≤ V(VOSENx+) - V(VOSENx-) ≤ 1.6V
Sink Current
0.5V≤ V(VOSENx+) - V(VOSENx-) ≤ 1.6V
Slew Rate
VOSEN+ Bias Current
0.5V≤ V(VOSENx+) - V(VOSENx-) ≤ 1.6V,
Note 1
0.5 V < V(VOSENx+) < 1.6V
VOSEN- Bias Current
-0.3V ≤ VOSENx- ≤ 0.3V, All VID Codes
Low Voltage
V(VCCL) = 7V
High Voltage
V(VCCL) – V(VOUTx)
VDAC1 & VDAC2 Outputs
Source Currents
Includes I(OCSET)
Sink Currents
Includes I(OCSET)
MIN
-0.5
-1.5
0.85
550
190
100
-10%
0.575
30
-8
2
0.2
-1
3.0
-3
0.5
2
2
-8%
-11%
TYP
MAX
0.5
1.5
.95 1.05
650 750
300 410
175 250
See
Figure 2
0.600
50
+10%
0.625
1
1
1
1
70
08
30
0.4 0.6
8
4.7
01
6.4 9.0
03
1 1.7
12 18
48
30 50
30 50
250
0.5 1
3000*Vrosc(
V)/
ROSC(kΩ)
1000*Vrosc
V)/
ROSC(kΩ)
+8%
+11%
UNIT
%
%
V
mV
mV
kΩ
kHz
V
V
V
V
V
%
mV
mA
mA
MHz
V/µs
µA
MHz
mV
mA
mA
V/us
uA
uA
mV
V
µA
µA
Page 5 of 37
June 20, 2008
5 Page 
IR3523
SYSTEM THEORY OF OPERATION
PWM Control Method
The PWM block diagram of the xPHASE3TM architecture is shown in Figure 5. Feed-forward voltage mode control
with trailing edge modulation is used. A high-gain wide-bandwidth voltage type error amplifier in the Control IC is
used for the voltage control loop. Input voltage is sensed in phase ICs and feed-forward control is realized. The
PWM ramp slope will change with the input voltage automatically compensating for changes in the input voltage.
The input voltage can change due to variations in the silver box output voltage or due to the wire and PCB-trace
voltage drop related to changes in load current.
IR3523 CONTROL IC
CLOCK GENERATOR
CLKOUT
PHSOUT
PHSIN
GATE DRIVE
VOLTAGE
REMOTE SENSE
AMPLIFIER
ERROR
AMPLIFIER
+
VDAC
+
-
+
-
VOUT1
VDAC1
LGND
-
EAOUT1
FB1
RCP1
CCP11
CCP12
RFB12
CFB1
RFB11
IFB1
IROSC
VDRP1 AMP
+
-
Output 1 Only
VDRP1
IIN1
CDRP1 RDRP1
PHSOUT
CLKIN
PHSIN
EAIN
PHASE IC
CLK Q
D
PWM
LATCH
S
PWM
COMPARATOR
RESET
DOMINANT
-R
+
ENABLE
+
VID6
-
RAMP
DISCHARGE
CLAMP
BODY
BRAKING
COMPARATOR
+-
ISHARE
SHARE ADJUST
ERROR AMPLIFIER
+
-
3K
VID6
- VID6
+
DACIN
VID6
VID6 +
+
CURRENT
SENSE
AMPLIFIER
+
-
VCC
VCCH
GATEH
SW
VCCL
GATEL
PGND
CBST
CSIN+
CCS RCS
CSIN-
PHSOUT
CLKIN
PHSIN
EAIN
PHASE IC
CLK Q
D
PWM
LATCH
S
PWM
COMPARATOR
RESET
DOMINANT
-R
+
ENABLE
+
VID6
-
RAMP
DISCHARGE
CLAMP
BODY
BRAKING
COMPARATOR
+-
ISHARE
SHARE ADJUST
ERROR AMPLIFIER
+
-
VID6
- VID6
3K +
DACIN
VID6
VID6 +
+
CURRENT
SENSE
AMPLIFIER
+
-
VCC
VCCH
GATEH
SW
VCCL
GATEL
PGND
CBST
CSIN+
CCS RCS
CSIN-
VIN
VOSNS1+
VOUT1
COUT
GND
VOSNS1-
Figure 5 - PWM Block Diagram
Frequency and Phase Timing Control
The oscillator is located in the Control IC and the system clock frequency is programmable from 500kHz to 9MHZ
by an external resistor. The control IC system clock signal (CLKOUT) is connected to CLKIN of all the phase ICs.
The phase timing of the phase ICs is controlled by the daisy chain loop, where control IC phase clock output
(PHSOUT) is connected to the phase clock input (PHSIN) of the first phase IC, and PHSOUT of the first phase IC is
connected to PHSIN of the second phase IC, etc. and PHSOUT of the last phase IC is connected back to PHSIN of
the control IC. During power up, the control IC sends out clock signals from both CLKOUT and PHSOUT pins and
detects the feedback at PHSIN pin to determine the phase number and monitor any fault in the daisy chain loop.
Figure 6 shows the phase timing for a four phase converter.
Page 11 of 37
June 20, 2008
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet IR3523.PDF ] | |
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