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AD9261 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD9261
Beschreibung 30 MSPS to 160 MSPS Continuous Time Sigma-Delta ADC
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 29 Seiten
AD9261 Datasheet, Funktion
16-Bit, 10 MHz Bandwidth, 30 MSPS to
160 MSPS Continuous Time Sigma-Delta ADC
AD9261
FEATURES
SNR: 83 dB (85 dBFS) to 10 MHz input
SFDR: 87 dBc to 10 MHz input
Noise figure: 15 dB
Input impedance: 1 kΩ
Power: 340 mW
1.8 V analog supply operation
1.8 V to 3.3 V output supply
Selectable bandwidth
2.5 MHz/5 MHz/10 MHz
Output data rate: 30 MSPS to 160 MSPS
Integrated decimation filters
Integrated sample rate converter
On-chip PLL clock multiplier
On-chip voltage reference
Offset binary, Gray code, or twos complement data format
Serial control interface (SPI)
APPLICATIONS
Data acquisition
Automated test equipment
Instrumentation
Medical imaging
GENERAL DESCRIPTION
The AD9261 is a single 16-bit analog-to-digital converter
(ADC) based on a continuous time (CT) sigma-delta (Σ-Δ)
architecture that achieves 87 dBc of dynamic range over a 10 MHz
input bandwidth. The integrated features and characteristics
unique to the continuous time Σ-Δ architecture significantly
simplify its use and minimize the need for external components.
The AD9261 has a resistive input impedance that relaxes the
requirements of the driver amplifier. In addition, a 32× oversam-
pled fifth-order continuous time loop filter significantly attenuates
out-of-band signals and aliases, reducing the need for external
filters at the input.
An external clock input or the integrated integer-N PLL provides
the 640 MHz internal clock needed for the oversampled conti-
nuous time Σ-Δ modulator. On-chip decimation filters and sample
rate converters reduce the modulator data rate from 640 MSPS to a
user-defined output data rate from 30 MSPS to 160 MSPS,
enabling a more efficient and direct interface.
VIN+
VIN–
VREF
CFILT
FUNCTIONAL BLOCK DIAGRAM
AVDD
DRVDD
Σ -Δ
MODULATOR
LOW-PASS
DECIMATION
FILTER
SAMPLE
RATE
CONVERTER
CMOS
BUFFER
AD9261
PHASE
LOCKED
LOOP
SERIAL
INTERFACE
OR
D15
D0
PLL_
LOCKED
CLK+
CLK–
DCO
AGND
SDIO SCLK CSB DGND
Figure 1.
The digital output data is presented in offset binary, Gray code,
or twos complement format. A data clock output (DCO) is
provided to ensure proper timing with the receiving logic.
The AD9261 operates on a 1.8 V analog supply and a 1.8 V
to 3.3 V digital supply, consuming 340 mW. The AD9261 is
available in a 48-lead LFCSP and is specified over the industrial
temperature range (−40°C to +85°C).
PRODUCT HIGHLIGHTS
1. Continuous time Σ-Δ architecture efficiently achieves high
dynamic range and wide bandwidth.
2. Passive input structure reduces or eliminates the require-
ments for a driver amplifier.
3. An oversampling ratio of 32× and high order loop filter
provide excellent alias rejection reducing or eliminating the
need for antialiasing filters.
4. An integrated decimation filter, sample rate converter, PLL
clock multiplier, and voltage reference provide ease of use.
5. This part operates from a single 1.8 V analog power supply
and 1.8 V to 3.3 V output supply.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2010 Analog Devices, Inc. All rights reserved.






AD9261 Datasheet, Funktion
AD9261
DIGITAL SPECIFICATIONS
All power supplies set to 1.8 V, 640 MHz sample rate, 0.5 V internal reference, PLL disabled, 40 MSPS output data rate, AIN = −2.0 dBFS,
unless otherwise noted.
Table 4.
Parameter1
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Differential Input Voltage
Input Common-Mode Range
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUTS (SCLK)
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUTS (SDIO, CSB, RESET)
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
DIGITAL OUTPUTS
DRVDD = 3.3 V
High Level Output Voltage (VOH, IOH = 50 μA)
High Level Output Voltage (VOH, IOH = 0.5 mA)
Low Level Output Voltage (VOL, IOL = 1.6 mA)
Low Level Output Voltage (VOL, IOL = 50 μA)
DRVDD = 1.8 V
High Level Output Voltage (VOH, IOH = 50 μA)
High Level Output Voltage (VOH, IOH = 0.5 mA)
Low Level Output Voltage (VOL, IOL = 1.6 mA)
Low Level Output Voltage (VOL, IOL = 50 μA)
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Min Typ
Max
CMOS/LVPECL
0.4 0.8
2
0.3
0.450
0.5
−60 +60
−60 +60
20
1
1.2
0
−50
−10
30
2
DRVDD + 0.3
0.8
−75
+10
1.2
0
−10
+40
26
5
DRVDD + 0.3
0.8
+10
+135
Unit
V p-p
V
μA
μA
pF
V
V
μA
μA
pF
V
V
μA
μA
pF
Full 3.29
Full 3.25
Full
Full
Full 1.79
Full 1.75
Full
Full
V
V
0.2 V
0.05 V
V
V
0.2 V
0.05 V
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
Rev. 0 | Page 5 of 28

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AD9261 pdf, datenblatt
120
SFDR (dBFS)
100
SNR (dBFS)
80
60
SFDR (dB)
40
SNR (dB)
20
0
–100 –90 –80 –70 –60 –50 –40 –30 –20 –10
INPUT AMPLITUDE (dBFS)
0
Figure 14. Single-Tone SNR and SFDR vs. Input Amplitude with fIN = 2.4 MHz
–40
–50
–60
SFDR (dBc)
–70
–80
–90
–100
–110
SFDR (dB)
–120
–60
–50 –40 –30 –20
INPUT AMPLITUDE (dBFS)
–10
Figure 15. Two-Tone SFDR/IMD3 vs. Input Amplitude
with fIN1 = 2.1 MHz and fIN2 = 2.4 MHz
94
SFDR (dBc)
92
90
88
86
84 SNR (dBc)
82
80
20 40 60 80 100 120 140 160
OUTPUT DATA RATE (MSPS)
Figure 16: SNR/SFDR vs. Output Data Rate with fIN = 2.4 MHz
AD9261
110
105
100
95
SFDR (dBc)
90
85 SNR (dB)
80
0 1 2 3 4 5 6 7 8 9 10
FREQUENCY (MHz)
Figure 17. SNR/SFDR vs. Input Frequency
92
91 1.9V
90
89 1.8V
SFDR
88 1.7V
87
86
85
SNR
84
83
82
81
–60 –40 –20
0
20 40 60
TEMPERATURE (°C)
1.9V
1.8V
1.7V
80 100
Figure 18. SFDR/SNR vs. Temperature with fIN = 2.4 MHz
84.0
83.8
83.6
83.4
83.2
83.0
82.8
82.6
82.4
82.2
82.0
1.700
1.725
1.750 1.775 1.800 1.825 1.850
COMMON-MODE VOLTAGE (V)
1.875
1.900
Figure 19. SNR vs. Input Common Mode Voltage with fIN = 2.4 MHz
Rev. 0 | Page 11 of 28

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