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AD9164 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD9164
Beschreibung RF DAC and Direct Digital Synthesizer
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD9164 Datasheet, Funktion
Data Sheet
16-Bit, 12 GSPS,
RF DAC and Direct Digital Synthesizer
AD9164
FEATURES
fast hop modes, phase coherent fast frequency hopping (FFH) is
DAC update rate up to 12 GSPS (minimum)
enabled, with several modes to support multiple applications.
Direct RF synthesis at 6 GSPS (minimum)
In baseband mode, wide analog bandwidth capability combines
DC to 2.5 GHz in baseband mode
with high dynamic range to support DOCSIS 3.1 cable infrastruc-
DC to 6 GHz in 2× nonreturn-to-zero (NRZ) mode
ture compliance from the minimum of one carrier up to the full
1.5 GHz to 7.5 GHz in Mix-Mode
maximum spectrum of 1.791 GHz of signal bandwidth. A 2×
Bypassable interpolation
interpolator filter (FIR85) enables the AD9164 to be configured
2×, 3×, 4×, 6×, 8×, 12×, 16×, 24×
for lower data rates and converter clocking to reduce the overall
Excellent dynamic performance
system power and ease the filtering requirements. In Mix-Mode™
APPLICATIONS
Broadband communications systems
DOCSIS 3.1 cable modem termination system (CMTS)/
video on demand (VOD)/edge quadrature amplitude
modulation (EQAM)
Wireless communications infrastructure
W-CDMA, LTE, LTE-A, point to point
GENERAL DESCRIPTION
operation, the AD9164 can reconstruct RF carriers in the second
and third Nyquist zones up to 7.5 GHz while still maintaining
exceptional dynamic range. The output current can be programmed
from 8 mA to 38.76 mA. The AD9164 data interface consists of
up to eight JESD204B serializer/deserializer (SERDES) lanes
that are programmable in terms of lane speed and number of
lanes to enable application flexibility.
An SPI interface configures the AD9164 and monitors the status of
all registers. The AD9164 is offered in an 165-ball, 8 mm × 8 mm,
The AD91641 is a high performance, 16-bit digital-to-analog
0.5 mm pitch CSP_BGA package, and an 169-ball, 11 mm × 11 mm,
converter (DAC) and direct digital synthesizer (DDS) that
0.8 mm pitch, CSP_BGA package, including a leaded ball option.
supports update rates to 6 GSPS. The DAC core is based on a
quad-switch architecture coupled with a 2× interpolator filter
that enables an effective DAC update rate of up to 12 GSPS in
some modes. The high dynamic range and bandwidth makes
these DACs ideally suited for the most demanding high speed
radio frequency (RF) DAC applications.
The DDS consists of a bank of 32, 32-bit numerically controlled
oscillators (NCOs), each with its own phase accumulator. When
combined with a 100 MHz serial peripheral interface (SPI) and
PRODUCT HIGHLIGHTS
1. High dynamic range and signal reconstruction bandwidth
supports RF signal synthesis of up to 7.5 GHz.
2. Up to eight lanes JESD204B SERDES interface flexible in
terms of number of lanes and lane speed.
3. Bandwidth and dynamic range to meet DOCSIS 3.1
compliance and multiband wireless communications
standards with margin.
FUNCTIONAL BLOCK DIAGRAM
RESET IRQ
ISET VREF
SDIO
SDO
CS
SCLK
SERDIN0±
SERDIN7±
SYNCOUT±
SYSREF±
SPI
JESD
HB
HB
AD9164
HB
NCO
VREF
NRZ RZ MIX
INV
SINC
DAC
CORE
OUTPUT±
HB
TO JESD
CLOCK
2×,
TO DATAPATH
DISTRIBUTION
4×,
TX_ENABLE
Figure 1.
CLK±
1 Protected by U.S. Patents 6,842,132 and 7,796,971.
Rev. 0
Document Feedback
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com






AD9164 Datasheet, Funktion
Data Sheet
Parameter
SERDES Supply Currents
VDD_1P2 = 1.2 V
DVDD_1P2 = 1.2 V
PLL_LDO_VDD12 = 1.2 V
SYNC_VDD_3P3 = 3.3 V
NCO ONLY MODE, 5 GSPS
Analog Supply Currents
VDD25_DAC = 2.5 V
VDD12A = 1.2 V
VDD12_CLK = 1.2 V
VNEG_N1P2 = −1.2 V
Digital Supply Currents
DVDD = 1.2 V
IOVDD1 = 2.5 V
SERDES Supply Currents
VDD_1P2 = 1.2 V
DVDD_1P2 = 1.2 V
PLL_LDO_VDD12 = 1.2 V
SYNC_VDD_3P3 = 3.3 V
8 LANES, 4× INTERPOLATION (80%), 5 GSPS
Analog Supply Currents
VDD25_DAC = 2.5 V
VDD12A = 1.2 V
VDD12_CLK = 1.2 V
VNEG_N1P2 = −1.2 V
Digital Supply Currents
DVDD = 1.2 V (Includes VDD12_DCD/DLL)
DVDD = 1.2 V
IOVDD1 = 2.5 V
SERDES Supply Currents
VDD_1P2 = 1.2 V
DVDD_1P2 = 1.2 V
PLL_LDO_VDD12 = 1.2 V
SYNC_VDD_3P3 = 3.3 V
8 LANES, 3× INTERPOLATION (80%), 4.5 GSPS
Analog Supply Currents
VDD25_DAC = 2.5 V
VDD12A = 1.2 V
VDD12_CLK = 1.2 V
VNEG_N1P2 = −1.2 V
Digital Supply Currents
DVDD = 1.2 V
IOVDD1 = 2.5 V
SERDES Supply Currents
VDD_1P2 = 1.2 V
DVDD_1P2 = 1.2 V
PLL_LDO_VDD12 = 1.2 V
SYNC_VDD_3P3 = 3.3 V
Test Conditions/Comments
Includes VTT_1P2, BIAS_VDD_1P2
Connected to PLL_CLK_VDD12
Includes VDD12_DCD/DLL
Includes VTT_1P2, BIAS_VDD_1P2
Connected to PLL_CLK_VDD12
NCO on, FIR85 off (unless otherwise noted)
At 6 GSPS
NCO on, FIR85 off
NCO off, FIR85 on
NCO on, FIR85 on
NCO on, FIR85 on, at 6 GSPS
Includes VTT_1P2, BIAS_VDD_1P2
Connected to PLL_CLK_VDD12
NCO on, FIR85 on
Includes VDD12_DCD/DLL
IOVDD = 2.5 V
Includes VTT_1P2, BIAS_VDD_1P2
Connected to PLL_CLK_VDD12
Rev. 0 | Page 5 of 134
AD9164
Min Typ Max Unit
443.4
72.3
81.8
9.4
mA
mA
mA
mA
−119
93.7
10
340.6
−112
425.5
2.5
1.4
1.0
0.13
0.32
100 mA
150 µA
432 mA
mA
753 mA
2.7 mA
34 mA
14.1 mA
1.5 mA
0.43 mA
−127.4
102
80
340.5
408
−120.2
108
150
432.4
mA
µA
mA
mA
mA
665.4
706.5
894.6
1090
2.5
1033
2.7
mA
mA
mA
mA
mA
411.2 550 mA
52.1 73 mA
85.8 105 mA
9.3 11 mA
94
85
314.3
−112.1
175
948.5
2.5
432.3
62.3
84.7
9.2
mA
µA
mA
mA
mA
mA
mA
mA
mA
mA

6 Page









AD9164 pdf, datenblatt
Data Sheet
AD9164
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
A VNEG_N1P2 VDD25_DAC VNEG_N1P2 VNEG_N1P2 VDD25_DAC VDD25_DAC OUTPUT– OUTPUT+ VDD25_DAC VDD25_DAC VNEG_N1P2 VNEG_N1P2
VSS
VSS
ISET
A
B VSS
VSS
VDD25_DAC VNEG_N1P2 VNEG_N1P2 VDD25_DAC VDD25_DAC VDD25_DAC VDD25_DAC VNEG_N1P2 VNEG_N1P2 VDD25_DAC VDD12A
VDD12A
VREF
B
C CLK+
VSS
VDD25_DAC VNEG_N1P2 VNEG_N1P2 VDD25_DAC VDD25_DAC VNEG_N1P2 VNEG_N1P2 VDD25_DAC VBG_NEG
VNEG_N1P2 VDD25_DAC C
D CLK–
VSS
VSS
VSS
VSS
VSS
D
E VSS
VSS
VSS
VSS
VSS
VDD12_CLK E
F VDD12_CLK VDD12_CLK VDD12_CLK
G IRQ
VSS
VSS
H
VSS
TX_ENABLE
VSS
VSS
VSS
VSS
VSS
VSS
VDD12_DCD/ VDD12_DCD/
DLL
DLL
VSS
VDD12_
DCD/DLL
VDD12_
DCD/DLL
VSS
VSS
VSS
VSS
VSS
VDD12_CLK VDD12_CLK VDD12_CLK F
VSS
VSS
CS G
VSS
SDO
VSS
H
J SERDIN7+ VDD_1P2
RESET
VSS
VSS
VSS
VSS
VSS
SCLK
VDD_1P2 SERDIN0+ J
K SERDIN7– VDD_1P2
IOVDD
DVDD
DVDD
DVDD
DVDD
DVDD
SDIO
VDD_1P2 SERDIN0– K
L VSS
VSS
DVDD_1P2
DVDD_1P2
VSS
VSS
L
M SERDIN6+ VDD_1P2 VTT_1P2
VTT_1P2 VDD_1P2 SERDIN1+ M
N SERDIN6– VDD_1P2
SYSREF+ SYSREF–
VSS
VSS
PLL_CLK_ PLL_LDO_
VDD12
VDD12
VSS
SYNCOUT– SYNCOUT+
VDD_1P2 SERDIN1– N
P VSS
SYNC_
VDD_3P3
VDD_1P2
VDD_1P2
DNC
VDD_1P2
VDD_1P2
PLL_LDO_
BYPASS
VDD_1P2
VDD_1P2
DNC
VDD_1P2
VDD_1P2
SYNC_
VDD_3P3
VSS
P
R BIAS_VDD_
1P2
1
VSS
2
SERDIN5+ SERDIN5–
34
VSS
5
SERDIN4+ SERDIN4–
67
VSS
8
SERDIN3– SERDIN3+
9 10
VSS
11
SERDIN2– SERDIN2+
12 13
VSS
14
BIAS_
VDD_1P2
R
15
1.2V ANALOG SUPPLY V
2.5V ANALOG SUPPLY V
1.2V DAC SUPPLY V
GROUND
DNC = DO NOT CONNECT.
1.2V DAC CLK SUPPLY V
SERDES INPUT
SERDES 3.3V VCO SUPPLY V
SERDES 1.2V SUPPLY V
DAC RF SIGNALS
SYSREF±/SYNCOUT±
CMOS I/O
IOVDD
Figure 4. 165-Ball CSP_BGA Pin Configuration
REFERENCE
Table 12. 165-Ball CSP_BGA Pin Function Descriptions
Pin No.
Mnemonic
A1, A3, A4, A11, A12, B4, B5, B10, B11, C5, C6, C9, C10, C14 VNEG_N1P2
A2, A5, A6, A9, A10, B3, B6, B7, B8, B9, B12, C4, C7, C8, C11, VDD25_DAC
C15
A7 OUTPUT−
A8 OUTPUT+
A13, A14, B1, B2, C2, D2, D3, D13, D14, D15, E1, E2, E3, E13,
E14, F6, F7, F8, F9, F10, G2, G3, G8, G13, G14, H1, H3, H6,
H7, H8, H9, H10, H13, H15, J6, J7, J8, J9, J10, L1, L2, L14,
L15, N6, N7, N10, P1, P15, R2, R5, R8, R11, R14
VSS
A15 ISET
B13, B14
B15
VDD12A
VREF
C1, D1
C12
CLK+, CLK−
VBG_NEG
E15, F1, F2, F3, F13, F14, F15
G1
G6, G7, G9, G10
VDD12_CLK
IRQ
VDD12_DCD/DLL
Description
−1.2 V Analog Supply Voltage.
2.5 V Analog Supply Voltage.
DAC Negative Current Output.
DAC Positive Current Output.
Supply Return. Connect these pins to ground.
Reference Current. Connect this pin to VNEG_N1P2 with
a 9.6 kΩ resistor.
1.2 V Analog Supply Voltage.
1.2 V Reference Input/Output. Connect this pin to VSS
with a 1 µF capacitor.
Positive and Negative DAC Clock Inputs.
−1.2 V Reference. Connect this pin to VNEG_N1P2 with
a 0.1 µF capacitor.
1.2 V Clock Supply Voltage.
Interrupt Request Output (Active Low, Open Drain).
1.2 V Digital Supply Voltage.
Rev. 0 | Page 11 of 134

12 Page





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