PDF AD9152 Data sheet ( Hoja de datos )

Número de pieza	AD9152
Descripción	Digital-to-Analog Converter
Fabricantes	Analog Devices
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Data Sheet Dual, 16-Bit, 2.25 GSPS, TxDAC+ Digital-to-Analog Converter AD9152 FEATURES GENERAL DESCRIPTION Supports input data rates up to 1.125 GSPS Proprietary low spurious and distortion design Single carrier LTE 20 MHz bandwidth (BW), ACLR = 77 dBc at 180 MHz IF SFDR = 72 dBc at 150 MHz IF, −6 dBFS Flexible 4-lane JESD204B interface Multiple chip synchronization Fixed latency Data generator latency compensation Selectable 1×, 2×, 4×, and 8× interpolation filter Low power architecture Input signal power detection Emergency stop for downstream analog circuitry protection Transmit enable function allows extra power saving High performance, low noise, phase-locked loop (PLL) clock multiplier Digital inverse sinc filter and programmable finite impulse response (FIR) filter Low power: 1223 mW at 1.5 GSPS, 1406 mW at 2.0 GSPS, full operating conditions 56-lead LFCSP with exposed pad APPLICATIONS Wireless communications Multicarrier LTE and GSM base stations Wideband repeaters Software defined radios Wideband communications Point to point microwave radios LMDS/MMDS Transmit diversity, multiple input/multiple output (MIMO) Instrumentation Automated test equipment The AD9152 is a dual, 16-bit, high dynamic range digital-to- analog converter (DAC) that provides a maximum sample rate of 2.25 GSPS, permitting a multicarrier generation up to the Nyquist frequency. The DAC outputs are optimized to interface seam- lessly with the ADRF6720 analog quadrature modulator (AQM) from Analog Devices, Inc. An optional 3-wire or 4-wire serial port interface (SPI) provides for programming/readback of many internal parameters. The full-scale output current can be programmed over a range of 4 mA to 20 mA. The AD9152 is available in a 56-lead LFCSP. The AD9152 is a member of the TxDAC+® family. PRODUCT HIGHLIGHTS 1. Ultrawide signal bandwidth enables emerging wideband and multiband wireless applications. 2. Advanced low spurious and distortion design techniques provide high quality synthesis of wideband signals from baseband to high intermediate frequencies. 3. JESD204B Subclass 1 support simplifies multichip synchronization in software and hardware design. 4. Fewer pins for data interface width with the serializer/ deserializer (SERDES) JESD204B four-lane interface. 5. Programmable transmit enable function allows easy design balance between power consumption and wake-up time. 6. Small package size with an 8 mm × 8 mm footprint. FUNCTIONAL BLOCK DIAGRAM RF OUTPUT CTRL AMP AMP VGA QUAD MOD ADRF6720 0/90° PHASE SHIFTER LPF DUAL DAC DAC DAC JESD204B SYNC SYSREF LO_IN MOD_SPI Figure 1. AD9152 DAC SPI Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com 1 page AD9152 Data Sheet DETAILED FUNCTIONAL BLOCK DIAGRAM SERDIN3± SERDIN0± SYNCOUT+ SYNCOUT– PLL (40×) DIV DACCLK I/Q HB1 HB2 HB3 MODE CONTROL HB1 HB2 HB3 SYNCHRONIZATION LOGIC PDP JESD204B ERRORS SPI TXEN CONFIG REGISTERS CLOCK DISTRIBUTION AND CONTROL LOGIC PLL_CTRL NCO FINE MODULATION MODULUS DDS COARSE DDS ±(fDAC/4), ±(fDAC/8) × N DOWNSTREAM PROTECTION DAC ALIGN DETECT SERIAL I/O POWER-ON PORT RESET DACCLK PLL_LOCK DAC PLL PFIR INV SINC DIGITAL GAIN [10:0] PHASE ADJUST DITHER DC OFFSET AD9152 I DAC 16-BIT DACCLK Q DAC 16-BIT DIV (2, 4, 16, 32) REF AND BIAS SYSREF RCVR CLK RECIEVER REF RECIEVER IOUT+ IOUT– QOUT+ QOUT– I120 SYSREF+ SYSREF– DACCLK+ DACCLK– REFCLK+ REFCLK– Figure 2. Detailed Functional Block Diagram Rev. 0 \| Page 4 of 104 5 Page AD9152 Data Sheet AC SPECIFICATIONS AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, PLLVDD12 = 1.2 V, SVDD12 = 1.2 V, SDVDD12 = 1.2 V, VTT = 1.2 V, TA = −40°C to +85°C, IOUTFS = 20 mA, unless otherwise noted. Table 9. Parameter Test Conditions/Comments Min Typ Max Unit SPURIOUS-FREE DYNAMIC RANGE (SFDR) −6 dBFS single tone fDAC = 1966.08 MSPS fOUT = 20 MHz 76 dBc fOUT = 150 MHz 72 dBc fOUT = 180 MHz 68 dBc TWO-TONE THIRD INTERMODULATION DISTORTION (IMD) −6 dBFS fDAC = 983.04 MSPS fOUT = 30 MHz 86 dBc fOUT = 150 MHz 79 dBc fDAC = 1966.08 MSPS fOUT = 30 MHz 86 dBc fOUT = 180 MHz 78 dBc NOISE SPECTRAL DENSITY (NSD), SINGLE TONE 0 dBFS fDAC = 983.04 MSPS fOUT = 150 MHz −162.5 dBm/Hz fDAC = 1966.08 MSPS fOUT = 180 MHz −163 dBm/Hz 5 MHz BW LTE FIRST ADJACENT CHANNEL LEAKAGE RATIO (ACLR), SINGLE CARRIER 0 dBFS, PLL off fDAC = 1966.08 MSPS fOUT = 50 MHz 79 dBc fOUT = 150 MHz 77 dBc fOUT = 180 MHz 77 dBc 5 MHz BW LTE SECOND ACLR, SINGLE CARRIER 0 dBFS, PLL off fDAC = 1966.08 MSPS fOUT = 50 MHz 82 dBc fOUT = 150 MHz 81 dBc fOUT = 180 MHz 81 dBc Rev. 0 \| Page 10 of 104 11 Page

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