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PDF AD8158 Data sheet ( Hoja de datos )
| Número de pieza | AD8158 | |
| Descripción | 6.5 Gbps Quad Buffer Mux/Demux | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
Quad 2:1 mux/1:2 demux
Optimized for dc to 6.5 Gbps NRZ data
Per-lane P/N pair inversion for routing ease
Programmable input equalization
Compensates up to 40 inches of FR4
Loss-of-signal detection
Programmable output pre-emphasis up to 12 dB
Programmable output levels with squelch and disable
Accepts ac-coupled or dc-coupled differential CML inputs
50 Ω on-chip termination
1:2 demux supports unicast or bicast operation
Port-level loopback
Port or single lane switching
1.8 V to 3.3 V flexible core supply
User-settable I/O supply from VCC to 1.2 V
Low power, typically 2.0 W in basic configuration
100-lead LFCSP
−40°C to +85°C operating temperature range
APPLICATIONS
Low cost redundancy switch
SONET OC48/SDH16 and lower data rates
XAUI/GbE/FC/Infiniband over backplane
OIF CEI 6.25 Gbps over backplane
Serial data-level shift
4-/8-/12-lane equalizers or redrivers
GENERAL DESCRIPTION
The AD8158 is an asynchronous, protocol-agnostic, quad-lane
2:1 switch with a total of 12 differential CML inputs and
12 differential CML outputs. The signal path supports NRZ
signaling with data rates up to 6.5 Gbps per lane. Each lane
offers programmable receive equalization, programmable
output pre-emphasis, programmable output levels, and loss-of-
signal detection.
The nonblocking switch-core of the AD8158 implements a
2:1 multiplexer and 1:2 demultiplexer per lane and supports
independent lane switching through the four select pins,
SEL[3:0]. Each port is a four-lane link. Every lane implements
an asynchronous path supporting dc to 6.5 Gbps NRZ data,
fully independent of other lanes. The AD8158 has low latency
and very low lane-to-lane skew.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
6.5 Gbps
Quad Buffer Mux/Demux
AD8158
Ix_A[3:0]
Ix_B[3:0]
FUNCTIONAL BLOCK DIAGRAM
RECEIVE
EQUALIZATION
EQ
EQ
2:1
TRANSMIT
PRE-
EMPHASIS
Ox_C[3:0]
Ox_A[3:0]
Ox_B[3:0]
SCL
SDA
I2C_A0
I2C_A1
I2C_A2
TRANSMIT
PRE-
EMPHASIS
I2C
CONTROL
LOGIC
AD8158
1:2 EQ Ix_C[3:0]
QUAD
2:1
MULTIPLEXER/
1:2
DEMULTIPLEXER
RECEIVE
EQUALIZATION
TOGGLE
CONTROL
LOGIC
LB_A
LB_B
LB_C
PE_A
PE_B
PE_C
EQ_A[1:0]
EQ_B[1:0]
EQ_C[1:0]
SEL[3:0]
BICAST
SEL4G
RESETb
LOS_INT
Figure 1.
The main application of the AD8158 is to support redundancy
on both the backplane and the line interface sides of a serial
link. The demultiplexing path implements unicast and bicast
capability, allowing the part to support either 1 + 1 or 1:1
redundancy.
The AD8158 is also suited for testing high speed serial links
because of its ability to duplicate incoming data. In a port-
monitoring application, the AD8158 can maintain link-
connectivity with a pass-through connection from Port C to
Port A while sending a duplicate copy of the data to test
equipment on Port B.
The rich feature set of the AD8158 can be controlled either
through external toggle pins or by setting on-chip control
registers through the I2C interface.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2008–2009 Analog Devices, Inc. All rights reserved.
1 page  
AD8158
Parameter
Supply Current
ICC
VCC = 1.8 V
VCC = 3.3 V
ITTO
VTTO = 1.8 V
VTTO = 3.3 V
ITTI
IDVCC
THERMAL CHARACTERISTICS
Operating Temperature Range
θJA
θJC
Maximum Junction Temperature
LOGIC CHARACTERISTICS3
Input High (VIH)
Input Low (VIL)
Input High (VIH)
Input Low (VIL)
Output High (VOH)
Output Low (VOL)
Conditions
LB_x = 0, PE = 0 dB on all ports, default
LB_x = 1, PE = 6 dB on all ports, default
LB_x = 0, PE = 0 dB on all ports, default
LB_x = 1, PE = 6 dB on all ports, default
LB_x = 0, PE = 0 dB on all ports, default
LB_x = 1, PE = 6 dB on all ports, default
LB_x = 0, PE = 0 dB on all ports, default
LB_x = 1, PE = 6 dB on all ports, default
Still air; JEDEC 4-layer test board, exposed pad
soldered
Still air; thermal resistance through exposed pad
I2C, SDA, SCL, control pins
DVCC = 3.3 V
DVCC = 3.3 V
DVCC = 1.8 V
DVCC = 1.8 V
2 kΩ pull-up resistor to DVCC
IOL = +3 mA
Min Typ
370
730
400
780
128
367
134
388
10
2
−40
22.2
1.4
0.7 × DVCC
VEE
VEE
VEE
0.8 × DVCC
0.2 × DVCC
DVCC
1 Bicast is off, loopback is off on all ports, preemphasis is set to minimum on all ports, and equalization is set to minimum on all ports.
2 VICM is the input common-mode voltage.
3 EQ control pins (EQ_A[1:0], EQ_B[1:0], EQ_C[1:0]) require 5 kΩ in series when DVCC > VCC.
Max Unit
450 mA
850 mA
460 mA
860 mA
150 mA
420 mA
152 mA
422 mA
20 mA
4 mA
+85 °C
°C/W
°C/W
125 °C
DVCC
0.3 × DVCC
DVCC
0.4
V
V
V
V
V
V
Rev. B | Page 4 of 36
5 Page 
AD8158
TYPICAL PERFORMANCE CHARACTERISTICS
50Ω CABLES
DATA OUT 2
2
INPUT
PIN
50Ω CABLES
OUTPUT 2
2
PIN
PATTERN
GENERATOR
AD8158
TP1 AC-COUPLED
EVALUATION
BOARD
TP2
50Ω
HIGH SPEED
SAMPLING
OSCILLOSCOPE
Figure 4. Standard Test Circuit (No Channel)
25ps/DIV
Figure 5. 6.5 Gbps Input Eye (TP1 from Figure 4)
25ps/DIV
Figure 6. 6.5 Gbps Output Eye, No Channel (TP2 from Figure 4)
Rev. B | Page 10 of 36
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD8158.PDF ] | |
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