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AD7173-8 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD7173-8
Beschreibung Highly Integrated Sigma-Delta ADC
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD7173-8 Datasheet, Funktion
Data Sheet
Low Power, 8-/16-Channel, 31.25 kSPS,
24-Bit, Highly Integrated Sigma-Delta ADC
AD7173-8
FEATURES
APPLICATIONS
Low power, 8-/16-channel, highly integrated multiplexed
analog-to-digital converter (ADC)
Integration
Precision analog input buffers and reference input buffers
2.5 V precision reference (3.5 ppm/°C)
Cross point multiplexer (enable system diagnostic)
Process control: PLC/DCS modules
Voltage, current, temperature, and pressure measurement
Flow meters
Medical and scientific multichannel instrumentation
Seismic instrumentation
Chemical analysis instrumentation: chromatography
8 full differential or 16 single-ended channels
Clock oscillator
GPIO and GPO pins with automatic external mux control
Fast and flexible output rate: 1.25 SPS to 31.25 kSPS
Channel scan data rate: 6.21 kSPS/channel (161 µs settling)
Performance specifications
17.5 noise free bits at 31.25 kSPS
GENERAL DESCRIPTION
Fast settling, highly accurate, low power, 8-/16-channel,
multiplexed ADC for low bandwidth input signals with
integrated input buffers.
Integrated precision, 2.5 V, low drift (3.5 ppm/°C), band gap
reference and integrated oscillator.
24 noise free bits at 1.25 SPS
INL: ±3 ppm/FSR
85 dB rejection of 50 Hz and 60 Hz with 50 ms settling
Operates with either 3.3 V or5 V supply
Single supply
3.3 V or 5 V AVDD1, 2 V to 5 V AVDD2, and 2 V to 5 V IOVDD
Optional split supply
AVDD1 and AVSS ± 2.5 V or AVDD1 and AVSS ± 1.65 V
Current: 1.4 mA
Eight flexible setups with configurability for output data rate,
digital filter mode, offset/gain error correction, reference selection,
buffer enables and more. This per channel configurability extends
to the output data rate used for each channel when using
sinc5 + sinc1 filter.
Sinc5 + sinc1 filter maximizes channel scan rate, and sinc3 filter
maximizes resolution and enhanced 50 Hz/60 Hz rejection,
with four selectable options to maximize rejection.
3-/4-wire serial digital interface (Schmitt trigger on SCLK)
Integrated diagnostic features, including CRC, register checksum,
CRC error checking
temperature sensor, crosspoint multiplexer, burnout currents,
SPI, QSPI, MICROWIRE, and DSP compatible
and GPIOs/GPOs.
Package: 40-lead 6 mm × 6 mm LFCSP
Temperature range: −40°C to +105°C
FUNCTIONAL BLOCK DIAGRAM
AVDD1 AVDD2 REGCAPA
REF– REF+ REFOUT
IOVDD REGCAPD
1.8V
LDO
CROSSPOINT
MULTIPLEXER
REFERENCE
INPUT
BUFFERS
BUFFERED
PRECISION
REFERENCE
1.8V
LDO
AIN0/REF2–
AIN1/REF2+
AIN15
AIN16
AVDD ANALOG
INPUT
BUFFERS
Σ-Δ ADC
AVSS
I/O AND EXTERNAL
MUX CONTROL
INT
REF
DIGITAL
FILTER
SERIAL
INTERFACE
AND CONTROL
XTAL AND INTERNAL
CLOCK OSCILLATOR
CIRCUITRY
AD7173-8
CS
SCLK
DIN
DOUT/RDY
SYNC
ERROR
TEMPERATURE
SENSOR
AVSS
PDSW
GPIO0 GPIO1 GPO2 GPO3
XTAL1 XTAL2/CLKIO
Figure 1.
DGND
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2013–2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com






AD7173-8 Datasheet, Funktion
Data Sheet
AD7173-8
Parameter
Power Supply Rejection
(Line Regulation)
Load Regulation
Voltage Noise
Voltage Noise Density
Turn-On Settling Time
Long-Term Stability3
Short Circuit
EXTERNAL REFERENCE
Reference Input Voltage
Absolute Reference Input Voltage
Limits1
Buffers Disabled
Buffers Enabled
Average Reference Input Current
Buffers Disabled
Buffers Enabled
Average Reference Input Current Drift
External clock
Internal clock
Normal Mode Rejection1
Common-Mode Rejection
TEMPERATURE SENSOR
Accuracy
Sensitivity
BURNOUT CURRENTS
Source/Sink Current
BRIDGE POWER-DOWN SWITCH
RON
Allowable Currents
GENERAL-PURPOSE I/O (GPIO0, GPIO1,
GPO2, GPO3)
Input Mode Leakage Current1
Floating State Output Capacitance
AVDD1 − AVSS = 5 V
Output High Voltage, VOH1
Output Low Voltage, VOL1
Input High Voltage, VIH1
Input Low Voltage, VIL1
AVDD1 − AVSS = 3.3 V
Output High Voltage, VOH1
Output Low Voltage, VOL1
Input High Voltage, VIH1
Input Low Voltage, VIL1
CLOCK
Internal Clock
Frequency
Accuracy
Duty Cycle
Output Low Voltage, VOL
Output High Voltage, VOH
Crystal
Frequency
Start-Up Time
External Clock (CLKIO)
Duty Cycle1
Test Conditions/Comments
AVDD1 and AVDD2
∆VOUT/∆IL
eN, 0.1 Hz to 10 Hz
eN, 1 kHz
100 nF capacitor
1000 hours
ISC
Reference input = (REF+) − (REF−)
Buffers disabled
See the Rejection parameter
After user calibration at 25°C
Analog input buffers must be enabled
With respect to AVSS
ISOURCE = 200 µA
ISINK = 800 µA
ISOURCE = 200 µA
ISINK = 800 µA
Typical duty cycle 50:50 (maximum:minimum)
Rev. A | Page 5 of 64
Min
1
AVSS − 0.05
AVSS
−10
AVSS + 4
AVSS + 3
AVSS + 2.7
AVSS + 2
−2.5
0.8 × IOVDD
14
30:70
Typ
90
140
6.5
215
60
460
25
2.5
±9
±50
±5
±6
83
±2
477
±10
24
5
2
50:50
16
10
2
50:50
Max
AVDD1
Unit
dB
ppm/mA
µV rms
nV/√Hz
µs
ppm
mA
V
AVDD1 + 0.05 V
AVDD1
V
µA/V
nA
nA/V/°C
nA/V/°C
dB
°C
µV/°C
µA
Ω
16 mA
+10
AVSS + 0.4
AVSS + 0.7
AVSS + 0.27
AVSS + 0.45
µA
pF
V
V
V
V
V
V
V
V
+2.5
0.4
16.384
2.048
70:30
MHz
%
V
V
MHz
µs
MHz

6 Page









AD7173-8 pdf, datenblatt
Data Sheet
AD7173-8
Pin
No. Mnemonic
15 DIN
16 SCLK
17 CS
18 ERROR
19 SYNC
20 IOVDD
21 DGND
22 REGCAPD
23 GPIO0
24 GPIO1
25 GPO2
26 AIN4
27 AIN5
28 AIN6
29 AIN7
30 AIN8
31 AIN9
32 AIN10
33 AIN11
34 AIN12
35 AIN13
36 AIN14
37 AIN15
38 GPO3
39 REF−
40 REF+
EP
Type1
DI
DI
DI
DI/O
DI
P
P
AO
DI/O
DI/O
DO
AI
AI
AI
AI
AI
AI
AI
AI
AI
AI
AI
AI
DO
AI
AI
P
Description
Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the
control registers in the ADC, with the register address (RA) bits of the communications register identifying
the appropriate register. Data is clocked in on the rising edge of SCLK.
Serial Clock Input. This serial clock input is for data transfers to and from the ADC. SCLK has a Schmitt
trigger input, making the interface suitable for opto-isolated applications.
Chip Select Input. This is an active low logic input used to select the ADC. CS can be used to select the ADC
in systems with more than one device on the serial bus. CS can be hardwired low, allowing the ADC to operate
in 3-wire mode with SCLK, DIN, and DOUT used to interface with the device. When CS is high, the
DOUT/RDY output is tristated.
This pin can be used in one of the following three modes:
Active low error input mode. This mode sets the ADC_ERROR bit in the STATUS register.
Active low, open-drain error output mode. The STATUS register error bits are mapped to the ERROR pin.
The ERROR pins of multiple devices can be wired together to a common pull-up resistor so that an error on
any device can be observed.
General-purpose output mode. The status of the pin is controlled by the ERR_DAT bit in the GPIOCON register.
The pin is referenced between IOVDD and DGND, as opposed to the AVDD1 and AVSS levels used by the
GPIO1 and GPIO2 pins. The ERROR pin has an active pull-up in this case.
Synchronization Input. Allows synchronization of the digital filters and analog modulators when using
multiple AD7173-8 devices.
Digital I/O Supply Voltage. IOVDD voltage ranges from 2 V to 5 V. IOVDD is independent of AVDD1 and
AVDD2. For example, IOVDD can be operated at 3.3 V when AVDD1 or AVDD2 equals 5 V, or vice versa. If
AVSS is set to −2.5 V, the voltage on IOVDD must not exceed 3.6 V.
Digital Ground.
Digital LDO Regulator Output. This pin is for decoupling purposes only. Decouple this pin to DGND using
a 1 µF capacitor.
General-Purpose Input/Output. Logic input/output on this this pin is referred to the AVDD1 and AVSS supplies.
General-Purpose Input/Output. Logic input/output on this this pin is referred to the AVDD1 and AVSS supplies.
General-Purpose Output. Logic output on this this pin is referred to the AVDD1 and AVSS supplies.
Analog Input 4. Selectable through cross point mux.
Analog Input 5. Selectable through cross point mux.
Analog Input 6. Selectable through cross point mux.
Analog Input 7. Selectable through cross point mux.
Analog Input 8. Selectable through cross point mux.
Analog Input 9. Selectable through cross point mux.
Analog Input 10. Selectable through cross point mux.
Analog Input 11. Selectable through cross point mux.
Analog Input 12. Selectable through cross point mux.
Analog Input 13. Selectable through cross point mux.
Analog Input 14. Selectable through cross point mux.
Analog Input 15. Selectable through cross point mux.
General-Purpose Output. Logic output on this this pin is referred to the AVDD1 and AVSS supplies.
Reference 1 Input Negative Terminal. REF− can span from AVSS to AVDD1 − 1 V. Reference 1 can be
selected through the REFSEL bits in the SETUP CONFIGURATION register.
Reference 1 Input Positive Terminal. An external reference can be applied between REF+ and REF−. REF+
can span from AVDD1 to AVSS + 1 V. Reference 1 can be selected through the REFSEL bits in the SETUP
CONFIGURATION register.
Exposed Pad. The exposed pad should be soldered to a similar pad on the PCB under the exposed paddle
to confer mechanical strength to the package and for heat dissipation. The exposed pad must be connected
to AVSS through this pad on the PCB.
1 AI = analog input, AO = analog output, DI/O = bidirectional digital input/output, DO = digital output, DI = digital input, P = power supply.
Rev. A | Page 11 of 64

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