Datenblatt-pdf.com


AD7172-2 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD7172-2
Beschreibung Sigma-Delta ADC
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD7172-2 Datasheet, Funktion
Data Sheet
Low Power, 24-Bit, 31.25 kSPS, Sigma-Delta
ADC with True Rail-to-Rail Buffers
AD7172-2
FEATURES
GENERAL DESCRIPTION
Fast and flexible output rate: 1.25 SPS to 31.25 kSPS
Channel scan data rate of 6.21 kSPS/channel (161 µs settling)
Performance specifications
17.2 noise free bits at 31.25 kSPS
24 noise free bits at 5 SPS
INL: ±2 ppm of FSR
85 dB rejection of 50 Hz and 60 Hz with 50 ms settling
User configurable input channels
2 fully differential channels or 4 single-ended channels
Crosspoint multiplexer
On-chip 2.5 V reference (±2 ppm/°C drift)
True rail-to-rail analog and reference input buffers
Internal or external clock
Power supply
AVDD1 = 3.0 V to 5.5 V, AVDD2 = IOVDD = 2 V to 5.5 V
Split supply with AVDD1 and AVSS at ±2.5 V or ±1.65 V
ADC current: 1.5 mA
Temperature range: −40°C to +105°C
3- or 4-wire serial digital interface (Schmitt trigger on SCLK)
Serial port interface (SPI), QSPI-, MICROWIRE-, and DSP-
compatible
APPLICATIONS
Process control: PLC/DCS modules
Temperature and pressure measurement
Medical and scientific multichannel instrumentation
Chromatography
The AD7172-2 is an intelligent, low noise, low power, multiplexed,
Σ-Δ analog-to-digital converter (ADC) with 2- or 4-channel
(fully differential/single-ended) inputs for low bandwidth
signals. The AD7172-2 has a maximum channel scan rate of
6.21 kSPS (161 µs) for fully settled data. The output data rates
range from 1.25 SPS to 31.25 kSPS.
The AD7172-2 integrates key analog and digital signal condition-
ing blocks to allow users to configure an individual setup for each
analog input channel in use via the SPI. Integrated true rail-to-rail
buffers on the analog inputs and external reference inputs provide
easy to drive high impedance inputs. The precision 2.5 V low drift
(2 ppm/°C) band gap internal reference (with an output reference
buffer) adds embedded functionality to reduce the external
component count.
The digital filter allows simultaneous 50 Hz and 60 Hz rejection
at a 27.27 SPS output data rate. The user can switch between
different filter options according to the demands of each channel in
the application, with further digital processing functions such as
offset and gain calibration registers, which are also configurable on
a per channel basis. General-purpose inputs/outputs (GPIOs)
control external multiplexers synchronous to the ADC conversion
timing.
The specified operating temperature range is −40°C to +105°C.
The AD7172-2 is in a 24-lead TSSOP package.
Note that, throughout this data sheet, the dual function pin
names are referenced by the relevant function only.
FUNCTIONAL BLOCK DIAGRAM
AVDD1 AVDD2 REGCAPA
REF– REF+ REFOUT
IOVDD REGCAPD
CROSSPOINT
MULTIPLEXER
1.8V
LDO
AIN0
AIN1
AIN2
AVDD
AVDD1
AVSS
RAIL-TO-RAIL
REFERENCE
INPUT BUFFERS
Σ-Δ ADC
BUFFERED
PRECISION
REFERENCE
INT
REF
DIGITAL
FILTER
1.8V
LDO
SERIAL
INTERFACE
AND CONTROL
AIN3
AIN4
RAIL-TO-RAIL
ANALOG INPUT
AVSS
BUFFERS
TEMPERATURE
SENSOR
GPIO AND
MUX
I/O CONTROL
XTAL AND INTERNAL
CLOCK OSCILLATOR
CIRCUITRY
AD7172-2
CS
SCLK
DIN
DOUT/RDY
SYNC/ERROR
AVSS
GPIO0 GPIO1
XTAL1 XTAL2/CLKIO
Figure 1.
DGND
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2014–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com






AD7172-2 Datasheet, Funktion
Data Sheet
Parameter
EXTERNAL REFERENCE INPUTS
Differential Input Range
Absolute Voltage Limits1
Input Buffers Disabled
Input Buffers Enabled
REFIN Input Current
Input Buffers Disabled
Input Current
Input Current Drift
Input Buffers Enabled
Input Current
Input Current Drift
Normal Mode Rejection1
Common-Mode Rejection
TEMPERATURE SENSOR
Accuracy
Sensitivity
BURNOUT CURRENTS
Source/Sink Current
GPIO (GPIO0, GPIO1)
Input Mode Leakage
Current1
Floating State Output
Capacitance
Output High Voltage, VOH1
Output Low Voltage, VOL1
Input High Voltage, VIH1
Input Low Voltage, VIL1
CLOCK
Internal Clock
Frequency
Accuracy
Duty Cycle
Output Low Voltage, VOL
Output High Voltage, VOH
Crystal
Frequency
Startup Time
External Clock (CLKIO)
Duty Cycle1
LOGIC INPUTS
Input High Voltage, VINH1
Input Low Voltage, VINL1
Hysteresis1
Leakage Currents
Test Conditions/Comments
VREF = (REF+) − (REF−)
External clock
Internal clock
See the Rejection parameter
After user calibration at 25°C
Analog input buffers must be enabled
With respect to AVSS
ISOURCE = 200 µA
ISINK = 800 µA
2 V ≤ IOVDD < 2.3 V
2.3 V ≤ IOVDD ≤ 5.5 V
2 V ≤ IOVDD < 2.3 V
2.3 V ≤ IOVDD ≤ 5.5 V
IOVDD ≥ 2.7 V
IOVDD < 2.7 V
Min Typ
1 2.5
AVSS − 0.05
AVSS
−10
AVSS + 4
AVSS + 3
±9
±100
±0.75
±100
±0.25
95
±2
477
±10
5
−2.5%
2
50
0.8 × IOVDD
14 16
10
2
30 50
0.65 × IOVDD
0.7 × IOVDD
0.08
0.04
−10
AD7172-2
Max
AVDD1
AVDD1 + 0.05
AVDD1
Unit
V
V
V
+10
AVSS + 0.4
AVSS + 0.7
µA/V
pA/V/°C
nA/V/°C
nA
nA/°C
dB
°C
µV/K
µA
µA
pF
V
V
V
V
+2.5%
0.4
16.384
2.048
70
0.35 × IOVDD
0.7
0.25
0.2
+10
MHz
%
%
V
V
MHz
µs
MHz
%
V
V
V
V
V
V
µA
Rev. A | Page 5 of 60

6 Page









AD7172-2 pdf, datenblatt
Data Sheet
AD7172-2
Pin No.
15
16
17
18
19
20
21
22
23
24
Mnemonic
SYNC/ERROR
IOVDD
DGND
REGCAPD
GPIO0
GPIO1
AIN0
AIN1
AIN2
AIN3
Type1
DI/O
P
P
AO
DI/O
DI/O
AI
AI
AI
AI
Description
Synchronization Input/Error Input/Output. This pin can be switched between a logic input and a logic
output in the GPIOCON register. When synchronization input (SYNC) is enabled, this pin allows
synchronization of the digital filters and analog modulators when using multiple AD7172-2 devices.
For more information, see the Synchronization section. When the synchronization input is disabled,
this pin can be used in one of the following three modes:
Active low error input mode: this mode sets the ADC_ERROR bit in the status register.
Active low, open-drain error output mode: the status register error bits are mapped to the ERROR
output. The SYNC/ERROR pins of multiple devices can be wired together to a common pull-up resistor
so that an error on any device can be observed.
General-purpose output mode: the status of the pin is controlled by the ERR_DAT bit in the GPIOCON
register. The pin is referenced between IOVDD and DGND, as opposed to the AVDD1 and AVSS levels
used by the GPIOx pins. The pin has an active pull-up in this case.
Digital Input/Output Supply Voltage. The IOVDD voltage ranges from 2 V to 5.5 V. IOVDD is
independent of AVDD2. For example, IOVDD can be operated at 3 V when AVDD2 equals 5 V, or vice
versa. If AVSS is set to −2.5 V, the voltage on IOVDD must not exceed 3.6 V.
Digital Ground.
Digital LDO Regulator Output. This pin is for decoupling purposes only. Decouple this pin to DGND
using a 1 µF and a 0.1 µF capacitor.
General-Purpose Input/Output 0. The pin is referenced between the AVDD1 and AVSS levels.
General-Purpose Input/Output 1. The pin is referenced between the AVDD1 and AVSS levels.
Analog Input 0. Analog Input 0 is selectable through the crosspoint multiplexer.
Analog Input 1. Analog Input1 is selectable through the crosspoint multiplexer.
Analog Input 2. Analog Input 2 is selectable through the crosspoint multiplexer.
Analog Input 3. Analog Input 3 is selectable through the crosspoint multiplexer.
1 AI is analog input, AO is analog output, DI/O is bidirectional digital input/output, DO is digital output, DI is digital input, and P is power supply.
Rev. A | Page 11 of 60

12 Page





SeitenGesamt 30 Seiten
PDF Download[ AD7172-2 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
AD7172-2Sigma-Delta ADCAnalog Devices
Analog Devices

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche