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AD7091R-4 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD7091R-4
Beschreibung 12-Bit SAR ADC
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD7091R-4 Datasheet, Funktion
Data Sheet
2-/4-/8-Channel, 1 MSPS,
Ultralow Power, 12-Bit SAR ADC
AD7091R-2/AD7091R-4/AD7091R-8
FEATURES
Ultralow system power
Flexible power/throughput rate management
Normal mode
1.4 mW at 1 MSPS
Power-down mode
550 nA typical at VDD = 5.25 V
435 nA typical at VDD = 3 V
Programmable ALERT interrupt pin (4-/8-channel models)
High performance
1 MSPS throughput with no latency/pipeline delay
SNR: 70 dB typical at 10 kHz input frequency
THD: −80 dB typical at 10 kHz input frequency
INL: ±0.7 LSB typical, ±1.0 LSB maximum
Small system footprint
On-chip accurate 2.5 V reference, 5 ppm/°C typical drift
MUXOUT/ADCIN to allow single buffer amplifier
Daisy-chain mode
16-lead, 20-lead, and 24-lead 4 mm × 4 mm LFCSP packages
16-lead, 20-lead, and 24-lead TSSOP packages
Easy to use
SPI/QSPI™/MICROWIRE™/DSP compatible digital interface
Integrated programmable channel sequencer
BUSY indication available (4-/8-channel models)
Built in features for control and monitoring applications
GPOx pins available (4-/8-channel models)
Wide operating range
Temperature range: −40°C to +125°C
Specified for VDD of 2.7 V to 5.25 V
APPLICATIONS
Battery-powered systems
Personal digital assistants
Medical instruments
Mobile communications
Instrumentation and control systems
Data acquisition systems
Optical sensors
Diagnostic/monitoring functions
Rev. C
Document Feedback
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responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
FUNCTIONAL BLOCK DIAGRAM
MUXOUT ADCIN VDD
REFIN/
REFOUT
REGCAP
VIN0
VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
VIN7
I/P
MUX
CHANNEL
SEQUENCER
2.5V
VREF
T/H
12-BIT
SUCCESSIVE
APPROXIMATION
ADC
ON-CHIP
OSC
CONTROL LOGIC
AND REGISTERS
AD7091R-8
VDRIVE
RESET
CONVST
SDO
SDI
SCLK
CS
GND
Figure 1.
ALERT/
BUSY/
GPO0
GPO1
GND
GENERAL DESCRIPTION
The AD7091R-2/AD7091R-4/AD7091R-8 family is a multichannel
12-bit, ultralow power, successive approximation analog-to-
digital converter (ADC) that is available in two, four, or eight
analog input channel options. The AD7091R-2/AD7091R-4/
AD7091R-8 operate from a single 2.7 V to 5.25 V power supply
and are capable of achieving a sampling rate of 1 MSPS.
The AD7091R-2/AD7091R-4/AD7091R-8 family offers up to eight
single-ended analog input channels with a channel sequencer
that allows a preprogrammed selection of channels to be converted
sequentially. The AD7091R-2/AD7091R-4/ AD7091R-8 also
feature an on-chip conversion clock, an on-chip accurate 2.5 V
reference, and a high speed serial interface.
The AD7091R-2/AD7091R-4/AD7091R-8 have a serial port
interface (SPI) that allows data to be read after the conversion
while achieving a 1 MSPS throughput rate. The conversion process
and data acquisition are controlled using the CONVST pin.
The AD7091R-2/AD7091R-4/AD7091R-8 use advanced design
techniques to achieve ultralow power dissipation at high
throughput rates. They also feature flexible power management
options. An on-chip configuration register allows the user to set up
different operating conditions. These include power management,
alert functionality, busy indication, channel sequencing, and
general-purpose output pins. The MUXOUT and ADCIN pins
allow signal conditioning of the multiplexer output prior to
acquisition by the ADC.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2013–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com






AD7091R-4 Datasheet, Funktion
AD7091R-2/AD7091R-4/AD7091R-8
Timing Diagram
tCYC
CONVST
CS
SCLK
SDO
SDI
EOC
tCNVPW
tACQ
tCONVERT
tEOCCSL
tEN
TRISTATE
tHSDO
1
tSCLK
tSCLKH
23 4 56
tDSDO
tSCLKL
CH_ID2 CH_ID1 CH_ID0 ALERT DB11 DB10
7
DB9
tSSDISCLK
ADD4
ADD3
tHSDISCLK
ADD2 ADD1
ADD0
RW
DB9
Figure 4. Serial Port Timing
Data Sheet
tQUIET
15
DB1
16
tDIS
DB0
TRISTATE
DB1
DB0
Rev. C | Page 6 of 42

6 Page









AD7091R-4 pdf, datenblatt
AD7091R-2/AD7091R-4/AD7091R-8
Data Sheet
Pin No.
TSSOP
LFCSP
20 18
Mnemonic
SDI
21 19 SDO
22 20 SCLK
23 21 CONVST
24 22 VDRIVE
Not 25
applicable
EPAD
Description
Serial Data Input Bus. Data to be written to the on-chip control registers is provided on this input.
Data is clocked into the registers on the falling edge of the SCLK input. Provide data MSB first.
Serial Data Output Bus. The conversion output data is supplied to this pin as a serial data
stream. The bits are clocked out on the falling edge of the SCLK input, and 13 SCLKs are
required to access the data. The data is provided MSB first.
Serial Clock. This pin acts as the serial clock input.
Convert Start Input Signal. Edge triggered logic input. The falling edge of CONVST places the
track-and-hold mode into hold mode and initiates a conversion.
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the
interface operates. Connect decoupling capacitors between VDRIVE and GND. Typical
recommended values are 10 µF and 0.1 µF. The voltage range on this pin is 1.8 V to 5.25 V and
may be different to the voltage range at VDD.
Exposed Pad. The exposed pad is not connected internally. It is recommended that the pad be
soldered to GND.
Rev. C | Page 12 of 42

12 Page





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