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AD805 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD805
Beschreibung Data Retiming Phase-Locked Loop
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 12 Seiten
AD805 Datasheet, Funktion
a
Data Retiming
Phase-Locked Loop
AD805*
FEATURES
CLOCK RECOVERY AND
155 Mbps Clock Recovery and Data Retiming
DATA RETIMING APPLICATION
Permits CCITT G.958 Type A Jitter Tolerance
Permits CCITT G.958 Type B Jitter Transfer
Random Jitter: 0.6؇ rms
Pattern Jitter: Virtually Eliminated
Jitter Peaking: Fundamentally None
DATA
INPUT
VOLTAGE
CONTROLLED
PHASE
SHIFTER
PHASE
DETECTOR
LOOP
FILTER
GAIN
Acquisition: 30 Bit Periods
Accepts NRZ Data without Preamble
Single Supply Operation: –5.2 V or +5 V
10 KH ECL Compatible
PRODUCT DESCRIPTION
The AD805 is a data retiming phase-locked loop designed for
Ouse with a Voltage-Controlled Crystal Oscillator (VCXO) to
perform clock recovery and data retiming on Nonreturn to Zero
B(NRZ) data. The circuit provides clock recovery and data
Sretiming on standard telecommunications STS-3 or STM-1
data (155.52 Mbps). A Vectron C0-434Y Series VCXO circuit
Ois used with the AD805 for specification purposes. Similar
circuit performance can be obtained using other commercially
Lavailable VCXO circuits. The AD805-VCXO circuit used for
Eclock recovery and data retiming can also be used for large
factor frequency multiplication.
TEThe AD805-VCXO circuit meets or exceeds CCITT G.958
RETIMING
MODULE
VCXO
(EXTERNAL)
AD805
RECOVERED
CLOCK
RETIMED
DATA
phase shifter, phase detector, and loop filter, act to align input
data phase errors to the stable recovered clock provided by the
VCXO. The range of the voltage-controlled phase shifter, at
least 2 Unit Intervals (UI), and the bandwidth of this loop, at
roughly 3 MHz, provide the circuit with its wideband jitter
tolerance characteristic.
The circuit can acquire lock to input data very quickly, within
44 bit periods, due to the accuracy of the VCXO and the action
of the data retiming loop. Typical integrated second-order PLLs
take at least several thousand bit periods to acquire lock. This is
due to their having a wide tuning range VCO. Decreasing the
regenerator specifications for STM-I Type A jitter tolerance and loop damping of a traditional second-order PLL shortens the
STM-1 Type B jitter transfer. The simultaneous Type A, wide- length of the circuit’s acquisition time, but at the expense of
band jitter tolerance and Type B, narrow-band jitter transfer
greater jitter peaking.
allows the use of the AD805-VCXO circuit in a regenerative
application to overcome optical line system interworking limit-
ations based on signal retiming using Type A passive tuned
device technology such as Surface-Acoustic-Wave (SAW) or
dielectric resonator filters, with Type B active devices such as
Phase-Locked Loops (PLLs).
The AD805-VCXO circuit is a second- order PLL that has no
jitter peaking. The zero used to stabilize the control loop of the
traditional second-order PLL effects the closed-loop transfer
function, causing jitter peaking in the jitter transfer function. In
the AD805-VCXO circuit, the zero needed to stabilize the loop
is implemented in the feedback path, in the voltage-controlled
The circuit VCXO provides a stable and accurate clock fre-
phase shifter. Placing the zero in the feedback path results in
quency signal with or without input data. The AD805 works
fundamentally no jitter peaking since the zero is absent from the
with the VCXO to dynamically adjust the recovered clock fre-
closed-loop transfer function.
quency to the frequency associated with the input data. This
frequency control loop tracks any low frequency component of
jitter on the input data. Since the circuit uses the VCXO for
clock recovery, it has a high Q for excellent wideband jitter at-
tenuation. The jitter transfer characteristic of the circuit is with-
in the jitter transfer requirements for a CCITT G.958 STM-1
Type B regenerator, which has a corner frequency of 30 kHz.
The AD805 overcomes the higher frequency jitter tolerance
limitations associated with traditional high Q, PLL based clock
and data recovery circuits through the use of its data retiming
loop. This loop, made up of the AD805’s voltage-controlled
*Protected by U.S. Patent No. 5,036,298
Output jitter, determined primarily by the VCXO, is a very low
0.6° rms. Jitter due to variations in input data density, pattern
jitter, is virtually eliminated in the circuit due to the AD805’s
patented phase detector.
The data retiming loop of the AD805 can be used with a passive
tuned circuit (155.52 MHz) such as a bandpass or a SAW filter
for clock recovery and data retiming. The data retiming loop
acts to servo the phase of the input data to the phase of the
recovered clock from the passive tuned circuit in this type of
application (see APPLICATIONS).
The AD805 uses 10 KH ECL levels and consumes 375 mW
from a +5 V or a –5.2 V supply. The device is specified for
REV. 0
operation over the industrial temperature range of –40°C to
+85°C and is available in a 20-pin plastic DIP.
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
© Analog Devices, Inc., 1996






AD805 Datasheet, Funktion
AD805
THEORY OF OPERATION
The AD805 is a delay- and phase- locked loop circuit for clock
recovery and data retiming from an NRZ-encoded data stream.
Figure 8 is a block diagram of the device shown with an external
VCXO. The AD805-VCXO circuit tracks the phase of the input
data using two feedback loops that share a common control
voltage. A high speed delay-locked loop path uses an on-chip
voltage-controlled phase shifter (VCPS) to track the high
frequency components of jitter on the input data. A separate
frequency control loop, using the external VCXO, tracks the low
frequency components of jitter on the input data.
peaking in any regenerative stage can contribute to hazardous
jitter accumulation.
JITTER OUT (dB)
JITTER IN
0 dB
ORDINARY PLL
Y(s)
X(s)
AD805 – VCXO
Z(s)
X(s)
1 sLOW sHIGH
LOG ω
AD805
τ
DATA
INPUT
VOLTAGE
CONTROLLED
PHASE
SHIFTER
PHASE
DETECTOR
LOOP
FILTER
INTERNAL LOOP
CONTROL VOLTAGE
RETIMING
MODULE
VCXO
(EXTERNAL)
VCXO
CONTROL VOLTAGE
RECOVERED
CLOCK
O RETIMED
DATA
BFigure 8. AD805-VCXO Clock Recovery Block Diagram
SThe two loops work together to null out phase error. For
example, when the clock is behind the data, the phase detector
Odrives the VCXO to a higher frequency and also increases the
delay through the VCPS. These actions serve to reduce the
Lphase error. The faster clock picks up phase while the delayed
Edata loses phase. When considering a static phase error, it is
easy to see that since the control voltage is developed by a loop
TEintegrator, the phase error will eventually reduce to zero.
Figure 10. Circuit Jitter Transfer Functions
The error transfer function, e(s)/X(s), has the same high pass
form as an ordinary phase-locked loop. This transfer function is
free to be optimized to give excellent wide-band jitter accommo-
dation since the jitter transfer function, Z(s)/X(s), provides the
narrow-band jitter filtering. The circuit has an error transfer
bandwidth of 3 MHz and a jitter transfer bandwidth of 10 kHz.
The circuit’s two loops contribute to overall jitter accommoda-
tion. At low frequencies, the integrator provides high gain so
that large jitter amplitudes can be tracked with small phase
errors between inputs of the phase detector. In this case, the
VCXO is frequency modulated and jitter is tracked as in an
ordinary phase-locked loop. The amount of low frequency jitter
that can be tracked is a function of the VCXO tuning range. A
wider tuning range corresponds to increased accommodation of
low frequency jitter. The internal loop control voltage remains
Another view of the circuit is that the AD805 VCPS implements
the zero that is required to stabilize a second order phase-locked
small for small phase errors, so the VCPS remains close to the
center of its range, contributing little to jitter accommodation.
loop and that the zero is placed in the feedback path so it does
At medium jitter frequencies, the gain and tuning range of the
not appear in the closed-loop transfer function. Jitter peaking in VCXO are not enough to track input jitter. In this case the
an ordinary second order phase-locked loop is caused by the VCXO control voltage input starts to hit the rails of its maxi-
presence of this zero in the closed-loop transfer function. Since mum voltage swing and the VCXO frequency output spends
the AD805-VCXO circuit is free of any zero in its closed-loop
most of the time at one or the other extreme of its tuning range.
transfer function, the circuit is free of jitter peaking.
The size of the VCXO tuning range therefore has a small effect
A linearized block diagram of the AD805-VCXO circuit is
shown in Figure 9. The two loops simultaneously provide wide-
band jitter accommodation and narrow-band jitter filtering.
on the jitter accommodation. The AD805 internal loop control
voltage is now larger, so the VCPS takes on the burden of
tracking input jitter. The VCPS range (in UI) is seen as the
plateau on the jitter tolerance curve (Figure 11). The VCPS has
Y a minimum range of 2 UI.
τ
100
X
PHASE
SHIFTER
+
e
+
PHASE
DETECTOR
K
1
s
INT
1
s
VCO
Z
10
Z(s)
X(s) =
s2
1
+ τs + 1
K
e(s)
X(s)
=
s2
s2+ Kτs + K
Figure 9. AD805-VCXO Circuit Linearized Block Diagram
The jitter transfer function, Z(s)/X(s), is second order and low
pass, providing excellent filtering. Note that the jitter transfer
function has no zero, unlike ordinary second-order phase-locked
loops. This means that the circuit has fundamentally no jitter
peaking (see Figure 10). Having no jitter peaking makes this
circuit ideal for signal regeneration applications where jitter
AD805-VCXO
JITTER TOLERANCE
1
CCITT TYPE A MASK
0.1
0.1
1
10
100
1000
10000
FREQUENCY – kHz
Figure 11. Jitter Accommodation Design Limit
–6– REV. 0

6 Page









AD805 pdf, datenblatt
AD805
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
20-Pin Plastic Dual In-Line Package
(N-20)
1.060 (26.90)
0.925 (23.50)
20 11 0.280 (7.11)
1 10 0.240 (6.10) 0.325 (8.25)
PIN 1
0.300 (7.62) 0.195 (4.95)
0.060 (1.52)
0.115 (2.93)
0.210 (5.33)
0.015 (0.38)
MAX
0.130
0.160 (4.06)
0.115 (2.93)
0.022 (0.558)
OBSOLETE0.014(0.356)
0.100
(2.54)
BSC
(3.30)
MIN
0.070 (1.77) SEATING
0.045 (1.15) PLANE
0.015 (0.381)
0.008 (0.204)
–12–
REV. 0

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