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PDF TXMC633 Data sheet ( Hoja de datos )
| Número de pieza | TXMC633 | |
| Descripción | Reconfigurable FPGA | |
| Fabricantes | TEWS | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de TXMC633 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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The Embedded I/O Company
TXMC633
Reconfigurable FPGA with 64 TTL I/O / 32
Differential I/O Lines
Version 1.0
User Manual
Issue 1.0.1
April 2015
TEWS TECHNOLOGIES GmbH
Am Bahnhof 7 25469 Halstenbek, Germany
Phone: +49 (0) 4101 4058 0 Fax: +49 (0) 4101 4058 19
1 page  
7.4.9 Generate Spartan6 Configuration Data ..................................................................................36
7.4.10 SPI-PROM Quad Mode enable ..............................................................................................36
7.4.11 Board Configuration FPGA .....................................................................................................37
7.5 Clocking .........................................................................................................................................38
7.5.1 FPGA Clock Sources ..............................................................................................................38
7.6 Front I/O Interface .........................................................................................................................39
7.7 Back I/O Interface..........................................................................................................................43
7.8 Memory ..........................................................................................................................................45
7.8.1 DDR3 SDRAM ........................................................................................................................45
7.8.2 SPI-Flash ................................................................................................................................47
7.9 Serial Number Allocation .............................................................................................................48
7.9.1 Device Addressing and Operation ..........................................................................................48
7.9.2 Read Operation.......................................................................................................................49
7.9.3 Write Operation.......................................................................................................................49
7.10 I/O Pull Configuration ...................................................................................................................50
7.11 User GPIO ......................................................................................................................................51
7.12 On-Board Indicators .....................................................................................................................52
7.13 Thermal Management ...................................................................................................................53
8 DESIGN HELP ............................................................................................................ 54
8.1 Example Design ............................................................................................................................54
9 INSTALLATION .......................................................................................................... 55
9.1 I/O Interface ...................................................................................................................................55
9.1.1 TTL I/O Interface.....................................................................................................................55
9.1.2 Differential I/O Interface..........................................................................................................56
9.1.3 Back I/O Interface ...................................................................................................................56
9.2 FPGA Debug Connector ...............................................................................................................57
9.2.1 Connecting TA900 to TXMC633 Debug Connector ...............................................................57
9.3 FPGA JTAG Connector ................................................................................................................58
10 PIN ASSIGNMENT – I/O CONNECTOR ..................................................................... 59
10.1 Overview ........................................................................................................................................59
10.2 X1 Front Panel I/O Connector ......................................................................................................59
10.2.1 Connector Type ......................................................................................................................59
10.2.2 Pin Assignment .......................................................................................................................60
10.3 Back I/O XMC Connector P14 ......................................................................................................61
10.3.1 Connector Type ......................................................................................................................61
10.3.2 Pin Assignment .......................................................................................................................61
10.4 P16 Back I/O Connector ...............................................................................................................62
10.4.1 Connector Type ......................................................................................................................62
10.4.2 Pin Assignment .......................................................................................................................62
10.5 X2 JTAG Header ............................................................................................................................63
10.5.1 Connector Type ......................................................................................................................63
10.5.2 Pin Assignment .......................................................................................................................63
10.6 X3 Debug-Connector ....................................................................................................................64
10.6.1 Connector Type ......................................................................................................................64
10.6.2 Pin Assignment .......................................................................................................................64
11 APPENDIX A............................................................................................................... 65
TXMC633 User Manual Issue 1.0.1
Page 5 of 71
5 Page 
3 Handling and Operation Instruction
3.1 ESD Protection
The TXMC633 is sensitive to static electricity. Packing, unpacking
and all other handling of the TXMC633 has to be done in an ESD/EOS
protected Area.
3.2 Thermal Considerations
Forced air cooling is recommended during operation. Without forced
air cooling, damage to the device can occur.
3.3 Assembling Hints
When disassembling the TXMC633 from carrier board please keep
the mechanical stress as low as possible.
TXMC633 User Manual Issue 1.0.1
Page 11 of 71
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet TXMC633.PDF ] | |
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