PDF AD9200 Data sheet ( Hoja de datos )

Número de pieza	AD9200
Descripción	CMOS A/D Converter
Fabricantes	Analog Devices
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No Preview Available ! a Complete 10-Bit, 20 MSPS, 80 mW CMOS A/D Converter AD9200 FEATURES CMOS 10-Bit, 20 MSPS Sampling A/D Converter Pin-Compatible with AD876 Power Dissipation: 80 mW (3 V Supply) Operation Between 2.7 V and 5.5 V Supply Differential Nonlinearity: 0.5 LSB Power-Down (Sleep) Mode Three-State Outputs Out-of-Range Indicator Built-In Clamp Function (DC Restore) Adjustable On-Chip Voltage Reference IF Undersampling to 135 MHz PRODUCT DESCRIPTION The AD9200 is a monolithic, single supply, 10-bit, 20 MSPS analog-to-digital converter with an on-chip sample-and-hold amplifier and voltage reference. The AD9200 uses a multistage differential pipeline architecture at 20 MSPS data rates and guarantees no missing codes over the full operating temperature range. The input of the AD9200 has been designed to ease the devel- opment of both imaging and communications systems. The user can select a variety of input ranges and offsets and can drive the input either single-ended or differentially. The sample-and-hold (SHA) amplifier is equally suited for both multiplexed systems that switch full-scale voltage levels in suc- cessive channels and sampling single-channel inputs at frequen- cies up to and beyond the Nyquist rate. AC coupled input signals can be shifted to a predetermined level, with an onboard clamp circuit (AD9200ARS, AD9200KST). The dynamic per- formance is excellent. The AD9200 has an onboard programmable reference. An external reference can also be chosen to suit the dc accuracy and temperature drift requirements of the application. A single clock input is used to control all internal conversion cycles. The digital output data is presented in straight binary output format. An out-of-range signal (OTR) indicates an over- flow condition which can be used with the most significant bit to determine low or high overflow. The AD9200 can operate with supply range from 2.7 V to 5.5 V, ideally suiting it for low power operation in high speed portable applications. The AD9200 is specified over the industrial (–40°C to +85°C) and commercial (0°C to +70°C) temperature ranges. PRODUCT HIGHLIGHTS Low Power The AD9200 consumes 80 mW on a 3 V supply (excluding the reference power). In sleep mode, power is reduced to below 5 mW. Very Small Package The AD9200 is available in both a 28-lead SSOP and 48-lead LQFP packages. Pin Compatible with AD876 The AD9200 is pin compatible with the AD876, allowing older designs to migrate to lower supply voltages. 300 MHz On-Board Sample-and-Hold The versatile SHA input can be configured for either single- ended or differential inputs. Out-of-Range Indicator The OTR output bit indicates when the input signal is beyond the AD9200’s input range. Built-In Clamp Function Allows dc restoration of video signals with AD9200ARS and AD9200KST. FUNCTIONAL BLOCK DIAGRAM CLAMP CLAMP IN CLK AVDD DRVDD STBY REV. E AIN REFTS REFBS REFTF REFBF VREF REFSENSE SHA SHA GAIN SHA GAIN SHA GAIN SHA GAIN A/D A/D D/A A/D D/A A/D D/A A/D D/A CORRECTION LOGIC OUTPUT BUFFERS 1V AD9200 AVSS DRVSS MODE THREE- STATE OTR D9 (MSB) D0 (LSB) Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999 1 page AD9200 ABSOLUTE MAXIMUM RATINGS* Parameter With Respect to Min Max Units AVDD AVSS DRVDD DRVSS AVSS DRVSS AVDD DRVDD MODE AVSS CLK AVSS Digital Outputs DRVSS AIN AVSS VREF AVSS REFSENSE AVSS REFTF, REFTB AVSS REFTS, REFBS AVSS Junction Temperature Storage Temperature Lead Temperature 10 sec –0.3 –0.3 –0.3 –6.5 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –65 +6.5 V +6.5 V +0.3 V +6.5 V AVDD + 0.3 V AVDD + 0.3 V DRVDD + 0.3 V AVDD + 0.3 V AVDD + 0.3 V AVDD + 0.3 V AVDD + 0.3 V AVDD + 0.3 V +150 °C +150 °C +300 °C Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may effect device reliability. ORDERING GUIDE Model Temperature Package Range Description Package Options AD9200JRS 0°C to +70°C 28-Lead SSOP RS-28 AD9200ARS –40°C to +85°C 28-Lead SSOP RS-28 AD9200JST 0°C to +70°C 48-Lead LQFP ST-48 AD9200KST 0°C to +70°C 48-Lead LQFP ST-48 AD9200JRSRL 0°C to +70°C 28-Lead SSOP (Reel) RS-28 AD9200ARSRL –40°C to +85°C 28-Lead SSOP (Reel) RS-28 AD9200JSTRL 0°C to +70°C 48-Lead LQFP (Reel) ST-48 AD9200KSTRL 0°C to +70°C 48-Lead LQFP (Reel) ST-48 AD9200 SSOP-EVAL Evaluation Board AD9200 LQFP-EVAL Evaluation Board RS = Shrink Small Outline; ST = Thin Quad Flatpack. AVDD DRVDD AVDD AVDD AVDD AVDD AVSS DRVSS DRVSS a. D0–D9, OTR AVSS AVSS b. Three-State, Standby, Clamp AVSS AVSS c. CLK AVDD AVSS d. AIN AVDD REFBS AVSS AVDD REFBF AVSS AVDD REFTF AVSS AVDD REFTS AVSS e. Reference AVDD AVDD AVDD AVDD AVSS AVSS AVSS f. CLAMPIN g. MODE h. REFSENSE Figure 2. Equivalent Circuits CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9200 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –4– AVSS i. VREF WARNING! ESD SENSITIVE DEVICE REV. E 5 Page AD9200 +FS –FS AIN +F/S RANGE OBTAINED FROM VREF PIN OR EXTERNAL REF REFTS REFBS –F/S RANGE OBTAINED FROM VREF PIN OR EXTERNAL REF SHA 10k⍀ AD9200 MODE (AVDD) REFTF 0.1␮F 10k⍀ 10k⍀ A2 A/D CORE 4.2k⍀ 0.1␮F TOTAL 10␮F 10k⍀ 0.1␮F REFBF a. Top/Bottom Mode V MIDSCALE AIN AD9200 MODE SHA AVDD/2 10k⍀ REFTF 0.1␮F REFTS REFBS 10k⍀ 10k⍀ A2 A/D CORE 4.2k⍀ 0.1␮F TOTAL 10␮F INTERNAL 10k⍀ REF 0.1␮F REFBF MIDSCALE OFFSET VOLTAGE IS DERIVED FROM INTERNAL OR EXTERNAL REF * MAXIMUM MAGNITUDE OF V IS DETERMINED BY INTERNAL REFERENCE b. Center Span Mode MAXIMUM MAGNITUDE OF V IS DETERMINED BY INTERNAL REFERENCE AND TURNS RATIO V AIN AVDD/2 SHA 10k⍀ AD9200 MODE AVDD/2 REFTF 0.1␮F REFTS REFBS 10k⍀ 10k⍀ A2 A/D CORE 4.2k⍀ 0.1␮F TOTAL 10␮F INTERNAL 10k⍀ REF 0.1␮F REFBF c. Differential Mode A1 1V AD9200 VREF (1V) REFSENSE AVSS 0.1␮F 1.0␮F d. 1 V Reference A1 1V AD9200 10k⍀ VREF (2V) 0.01␮F REFSENSE 1.0␮F 10k⍀ AVSS e. 2 V Reference A1 1V AD9200 VREF (= 1 + RA/RB) RA REFSENSE RB AVSS 0.1␮F 1.0␮F INTERNAL 10K REF RESISTORS ARE SWITCHED OPEN BY THE PRESENSE OF RA AND RB. f. Variable Reference (Between 1 V and 2 V) Figure 16. –10– A1 1V AD9200 VREF REFSENSE AVDD g. Internal Reference Disable (Power Reduction) REV. E 11 Page

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