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ADF4218L Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADF4218L
Beschreibung Dual Low Power Frequency Synthesizers
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 24 Seiten
ADF4218L Datasheet, Funktion
a
Dual Low Power
Frequency Synthesizers
ADF4217L/ADF4218L/ADF4219L
FEATURES
Total IDD: 7.1 mA
Bandwidth/RF 3.0 GHz
ADF4217L/ADF4218L, IF 1.1 GHz
ADF4219L, IF 1.0 GHz
2.6 V to 3.3 V Power Supply
1.8 V Logic Compatibility
Separate VP Allows Extended Tuning Voltage
Selectable Dual Modulus Prescaler
Selectable Charge Pump Currents
Charge Pump Current Matching of 1%
3-Wire Serial Interface
Power-Down Mode
APPLICATIONS
Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA)
Base Stations for Wireless Radio (GSM, PCS, DCS, WCDMA)
Wireless LANs
Communications Test Equipment
Cable TV Tuners (CATV)
GENERAL DESCRIPTION
The ADF4217L/ADF4218L/ADF4219L are low power dual
frequency synthesizers that can be used to implement local
oscillators in the up-conversion and down-conversion sections
of wireless receivers and transmitters. They can provide the LO
for both the RF and IF sections. They consist of a low noise
digital PFD (phase frequency detector), a precision charge pump, a
programmable reference divider, programmable A and B counters,
and a dual modulus prescaler (P/P + 1). The A and B counters,
in conjunction with the dual modulus prescaler (P/P + 1),
implement an N divider (N = BP + A). In addition, the 14-bit
reference counter (R Counter) allows selectable REFIN fre-
quencies at the PFD input. A complete PLL (phase-locked
loop) can be implemented if the synthesizers are used with an
external loop filter and VCOs (voltage controlled oscillators).
Control of all the on-chip registers is via a simple 3-wire interface
with 1.8 V compatibility. The devices operate with a power supply
ranging from 2.6 V to 3.3 V and can be powered down when
not in use.
IFINA
IFINB
ADF4217L
ADF4218L
ONLY
REFIN
CLOCK
DATA
LE
RFINA
RFINB
FUNCTIONAL BLOCK DIAGRAM
ADF4219L ONLY
NC VDD1 VDD2
VP1
VP2
N = BP + A
IF
PRESCALER
BUFFER
11(13)-BIT IF
B COUNTER
6(5)-BIT IF
A COUNTER
PHASE
COMPARATOR
ADF4217L/
ADF4218L/
ADF4219L
CHARGE
PUMP
CPIF
IF
LOCK
DETECT
22-BIT
DATA SDOUT
REGISTER
14(15)-BIT IF
R COUNTER
14(15)-BIT RF
R COUNTER
OUTPUT
MUX
MUXOUT
RF
LOCK
DETECT
N = BP + A
RF
PRESCALER
11(13)-BIT RF
B COUNTER
6(5)-BIT RF
A COUNTER
PHASE
COMPARATOR
CHARGE
PUMP
CPRF
REV. C
FEATURES IN ( ) REFER TO ADF4219L
NC = NO CONNECT
DGNDRF AGNDRF DGNDIF AGNDIF
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.






ADF4218L Datasheet, Funktion
ADF4217L/ADF4218L/ADF4219L
Mnemonic
VDD1
VP1
CPRF
DGNDRF
RFINA
RFINB
AGNDRF
REFIN
DGNDIF
MUXOUT
CLK
DATA
LE
AGNDIF
NC
IFINB
IFINA
DGNDIF
CPIF
VP2
VDD2
PIN FUNCTION DESCRIPTIONS
Function
Positive Power Supply for the RF Section. Decoupling capacitors to the analog ground plane should be placed as
close as possible to this pin. VDD1 should have a value of between 2.6 V and 3.3 V. VDD1 must have the same
potential as VDD2.
Power Supply for the RF Charge Pump. This should be greater than or equal to VDD.
Output from the RF Charge Pump. When enabled, this provides ± ICP to the external loop filter, which in turn
drives the external VCO.
Ground Pin for the RF Digital Circuitry
Input to the RF Prescaler. This low level input signal is normally ac-coupled to the external VCO.
Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane with a small
bypass capacitor, typically 100 pF.
Ground Pin for the RF Analog Circuitry
Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and an equivalent input resistance of
100 k. This input can be driven from a TTL or CMOS crystal oscillator, or can be ac-coupled.
Ground Pin for the IF Digital, Interface, and Control Circuitry
This multiplexer output allows either the IF/RF Lock Detect, the scaled RF, or the scaled Reference Frequency to
be accessed externally (Table V).
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the
22-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a
high impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four
latches; the latch is selected using the control bits.
Ground Pin for the IF Analog Circuitry
This pin is not connected internally (ADF4219L only).
Complementary Input to the IF Prescaler. This point should be decoupled to the ground plane with a small bypass
capacitor, typically 100 pF (ADF4217L/ADF4218L only).
Input to the IF Prescaler. This low level input signal is normally ac-coupled to the external VCO.
Ground Pin for the IF Digital, Interface, and Control Circuitry
Output from the IF Charge Pump. When enabled, this provides ± ICP to the external loop filter, which in turn drives
the external VCO.
Power Supply for the IF Charge Pump. This should be greater than or equal to VDD.
Positive Power Supply for the IF Interface and Oscillator Sections. Decoupling capacitors to the analog ground
plane should be placed as close as possible to this pin. VDD2 should have a value of between 2.6 V and 3.3 V.
VDD2 must have the same potential as VDD1.
–6– REV. C

6 Page









ADF4218L pdf, datenblatt
ADF4217L/ADF4218L/ADF4219L
Table III. ADF4219L Family Latch Summary
IF REFERENCE COUNTER LATCH
15-BIT REFERENCE COUNTER, R
CONTROL
BITS
DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
P4 P3 P2 P5 P1 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 C2 (0) C1 (0)
IF AB COUNTER LATCH
13-BIT B COUNTER
5-BIT A COUNTER
CONTROL
BITS
DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
P7 P6 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 A5 A4 A3 A2 A1 C2 (0) C1 (1)
RF REFERENCE COUNTER LATCH
15-BIT REFERENCE COUNTER, R
CONTROL
BITS
DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
P12 P11 P10 P13 P9 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 C2 (1) C1 (0)
RF AB COUNTER LATCH
13-BIT B COUNTER
5-BIT A COUNTER
CONTROL
BITS
DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
P16 P14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 A5 A4 A3 A2 A1 C2 (1) C1 (1)
–12–
REV. C

12 Page





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