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HI-3582A Schematic ( PDF Datasheet ) - HOLTIC

Teilenummer HI-3582A
Beschreibung 3.3V Terminal IC
Hersteller HOLTIC
Logo HOLTIC Logo 




Gesamt 17 Seiten
HI-3582A Datasheet, Funktion
July 2013
HI-3582A, HI-3583A
ARINC 429
3.3V Terminal IC with High-Speed Interface
GENERAL DESCRIPTION
The HI-3582A/HI-3583A from Holt Integrated Circuits are
silicon gate CMOS devices for interfacing a 16-bit parallel
data bus directly to the ARINC 429 serial bus. The
HI-3582A/HI-3583A design offers a high-speed host CPU
interface compared with the earlier HI-3582/HI-3583
products. The device provides two receivers each with
label recognition, 32 by 32 FIFO, and analog line receiver.
Up to 16 labels may be programmed for each receiver.
The independent transmitter has a 32 X 32 FIFO and a
built-in line driver. The status of all three FIFOs can be
monitored using the external status pins, or by polling the
HI-3582A/HI-3583A status register. Other features include
a programmable option of data or parity in the 32nd bit,
and the ability to unscramble the 32 bit word. Also,
versions are available with different values of input
resistance and output resistance to allow users to more
easily add external lightning protection circuitry.
The 16-bit parallel data bus exchanges the 32-bit ARINC
data word in two steps when either loading the transmitter
or interrogating the receivers. The databus and all control
signals are 3.3V CMOS compatible.
The HI-3582A/HI-3583A apply the ARINC protocol to the
receivers and transmitter. Timing is based on a 1 Mega-
hertz clock.
APPLICATIONS
• Avionics data communication
• Serial to parallel conversion
• Parallel to serial conversion
PIN CONFIGURATIONS (Top View)
(See page 14 for additional pin configuration)
See Note below
N/C - 1
D/R1 - 2
FF1 - 3
HF1 - 4
D/R2 - 5
FF2 - 6
HF2 - 7
SEL - 8
EN1 - 9
EN2 - 10
N/C - 11
BD15 - 12
BD14 - 13
BD13 - 14
BD12 - 15
BD11 - 16
HI-3582APCI
HI-3582APCT
HI-3582APCM
&
HI-3583APCI
HI-3583APCT
HI-3583APCM
48 - CWSTR
47 - ENTX
46 - N/C
45 - V+
44 - TXBOUT
43 - TXAOUT
42 - V-
41 - N/C
40 - FFT
39 - HFT
38 - TX/R
37 - PL2
36 - PL1
35 - BD00
34 - BD01
33 - N/C
(Note: All 3 VDD pins must be connected to the same 3.3V supply)
64 - Pin Plastic 9mm x 9mm
Chip-Scale Package
FEATURES
· ARINC specification 429 compatible
· High-speed 3.3V logic interface
· Dual receiver and transmitter interface
· Analog line driver and receivers connect directly to
ARINC bus
· Programmable label recognition
· On-chip 16 label memory for each receiver
· 32 x 32 FIFOs each receiver and transmitter
· Independent data rate selection for transmitter and
each receiver
· Status register
· Data scramble control
· 32nd transmit bit can be data or parity
· Self test mode
· Low power
· Industrial & extended temperature ranges
FF1 - 1
HF1 - 2
D/R2 - 3
FF2 - 4
HF2 - 5
SEL - 6
EN1 - 7
EN2 - 8
BD15 - 9
BD14 - 10
BD13 - 11
BD12 - 12
BD11 - 13
HI-3582APQI
HI-3582APQT
HI-3582APQM
&
HI-3583APQI
HI-3583APQT
HI-3583APQM
39 - N/C
38 - CWSTR
37 - ENTX
36 - V+
35 - TXBOUT
34 - TXAOUT
33 - V-
32 - FFT
31 - HFT
30 - TX/R
29 - PL2
28 - PL1
27 - BD00
(DS3582A Rev. C)
52 - Pin Plastic Quad Flat Pack (PQFP)
HOLT INTEGRATED CIRCUITS
www.holtic.com
07/13






HI-3582A Datasheet, Funktion
HI-3582A, HI-3583A
FUNCTIONAL DESCRIPTION (cont.)
Once a valid ARINC word is loaded into the FIFO, then EOS
clocks the data ready flag flip flop to a "1", D/R1 or D/R2 (or both)
will go low. The data flag for a receiver will remain low until both
ARINC bytes from that receiver are retrieved and the FIFO is
empty. This is accomplished by first activating EN with SEL, the
byte selector, low to retrieve the first byte and then activating EN
with SEL high to retrieve the second byte. EN1 retrieves data
from receiver 1 and EN2 retrieves data from receiver 2.
Up to 32 ARINC words may be loaded into each receiver’s FIFO.
The FF1 (FF2) pin will go low when the receiver 1 (2) FIFO is full.
Failure to retrieve data from a full FIFO will cause the next valid
ARINC word received to overwrite the existing data in FIFO
location 32. A FIFO half full flag HF1 (HF2) goes low if the FIFO
contains 16 or more received ARINC words. The HF1 (HF2) pin is
intended to act as an interrupt flag to the system’s external
microprocessor, allowing a 16 word data retrieval routine to be
performed, without the user needing to continually poll the
HI-3582A/HI-3583A status register bits.
LABEL RECOGNITION
The chip compares the incoming label to the stored labels if label
recognition is enabled. If a match is found, the data is processed.
If a match is not found, no indicators of receiving ARINC data are
presented. Note that 00(Hex) is treated in the same way as any
other label value. Label bit significance is not changed by the
status of control register bit CR15. Label bits BD00 - BD07 are
always compared to received ARINC bits 1 - 8 respectively.
LOADING LABELS
After a write that takes CR1 from 0 to 1, the next 16 writes of
data (PL pulsed low) load label data into each location of the
label memory from the BD00 - BD07 pins. The PL1 pin is used to
write label data for receiver 1 and PL2 for receiver 2. Note that
ARINC word reception is suspended during the label memory
write sequence.
READING LABELS
After the write that changes CR1 from 0 to 1, the next 16 data
reads of the selected receiver (EN taken low) are labels. EN1 is
used to read labels for receiver 1, and EN2 to read labels for
receiver 2. Label data is presented on BD0-BD7.
When writing to, or reading from the label memory, SEL must be a
one, all 16 locations should be accessed, and CR1 must be
written to zero before returning to normal operation. Label
recognition must be disabled (CR2/3=0) during the label read
sequence.
TRANSMITTER
FIFO OPERATION
The FIFO is loaded sequentially by first pulsing PL1 to load byte 1
and then PL2 to load byte 2. The control logic automatically loads
the 31 bit word (or 32 bit word if CR4=0) in the next available
position of the FIFO. If TX/R, the transmitter ready flag is high
(FIFO empty), then up to 32 words, each 31 or 32 bits long, may
be loaded. If TX/R is low, then only the available positions may be
loaded. If all 32 positions are full, the FFT flag is asserted and the
FIFO ignores further attempts to load data.
A transmitter FIFO half-full flag HFT is provided. When the
transmit FIFO contains less than 16 words, HFT is high,
indicating to the system microprocessor that a 16 ARINC word
block write sequence can be initiated.
In normal operation (CR4=1), the 32nd bit transmitted is a parity
bit. Odd or even parity is selected by programming control
register bit CR12 to a zero or one. If Cr4 is programmed to a 0,
then all 32-bits of data loaded into the transmitter FIFO are
treated as data and are transmitted.
CR4,12
32 BIT PARALLEL
LOAD SHIFT REGISTER
32 x 32 FIFO
DATA BUS
BIT CLOCK
PARITY
GENERATOR
WORD CLOCK
ADDRESS
LOAD
DATA AND
NULL TIMER
SEQUENCER
LINE DRIVER
BIT
AND
WORD GAP
COUNTER
START
SEQUENCE
WORD COUNTER
AND
FIFO CONTROL
INCREMENT
WORD COUNT
FIFO
LOADING
SEQUENCER
TXAOUT
TXBOUT
TEST
TX/R
HFT
FFT
ENTX
PL1
PL2
DATA
CLOCK
CR13
DATA CLOCK
DIVIDER
FIGURE 3. TRANSMITTER BLOCK DIAGRAM
CLK
TX CLK
HOLT INTEGRATED CIRCUITS
6

6 Page









HI-3582A pdf, datenblatt
HI-3582A, HI-3583A
DC ELECTRICAL CHARACTERISTICS
VDD = 3.3V , V+ = 10V, V- = -10V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified).
PARAMETER
ARINC INPUTS - Pins RIN1A, RIN1B, RIN2A, RIN2B
SYMBOL
CONDITIONS
LIMITS
UNIT
MIN TYP MAX
Differential Input Voltage:
(RIN1A to RIN1B, RIN2A to RIN2B)
ONE
ZERO
NULL
VIH
VIL
VNUL
Common mode voltages
less than ±4V with
respect to GND
6.5
-13.0
-2.5
10.0
-10.0
0
13.0
-6.5
2.5
V
V
V
Input Resistance:
Differential
To GND
To VDD
RI
RG
RH
12 80
12 45
12 40
KW
KW
KW
Input Current:
Input Sink
Input Source
IIH
IIL
-450
200 µA
µA
Input Capacitance:
(Guaranteed but not tested)
Differential CI (RIN1A to RIN1B, RIN2A to RIN2B)
To GND
CG
To VDD
CH
20 pF
20 pF
20 pF
BI-DIRECTIONAL INPUTS - Pins BD00 - BD15
Input Voltage:
Input Voltage HI
Input Voltage LO
VIH
VIL
70% VDD
V
30% VDD V
Input Current:
Input Sink
Input Source
IIH
IIL
1.5 µA
-1.5 µA
OTHER INPUTS
Input Voltage:
Input Voltage HI
Input Voltage LO
VIH
VIL
70% VDD
V
30% VDD V
Input Current:
Input Sink
Input Source
Pull-down Current (TEST Pin)
Pull-up Current (RSR Pin)
ARINC OUTPUTS - Pins TXAOUT, TXBOUT
IIH
IIL
IPD
IPU
1.5 µA
-1.5 µA
330 µA
-330
µA
ARINC output voltage (Ref. To GND)
One or zero
Null
VDOUT
VNOUT
No load and magnitude at pin,
VDD = 3.3 V
4.50 5.00 5.50 V
-0.25
0.25 V
ARINC output voltage (Differential)
One or zero
Null
VDDIF
VNDIF
No load and magnitude at pin,
VDD = 3.3 V
9.0 10.0 11.0 V
-0.5 0.5 V
ARINC output current
IOUT
80 mA
OTHER OUTPUTS
Output Voltage:
Logic "1" Output Voltage
Logic "0" Output Voltage
VOH
VOL
IOH = -100µA
IOL = 1.0mA
VDD - 0.2V
V
10% VDD V
Output Current:
(All Outputs & Bi-directional Pins)
Output Sink
Output Source
IOL
IOH
VOUT = 0.4V
VOUT = VDD - 0.4V
1.6
mA
-1.0 mA
Output Capacitance:
CO
15 pF
Operating Voltage Range
VDD
3.15
3.45 V
V+ 9.5 10.5 V
V- -9.5 -10.5 V
Operating Supply Current
VDD
IDD1 3.5 7 mA
V+ IDD2 7.5 10 mA
V- IEE1 5.5 10 mA
HOLT INTEGRATED CIRCUITS
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