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HI-3593 Schematic ( PDF Datasheet ) - HOLTIC

Teilenummer HI-3593
Beschreibung 3.3V ARINC 429 Dual Receiver / Single Transmitter
Hersteller HOLTIC
Logo HOLTIC Logo 




Gesamt 23 Seiten
HI-3593 Datasheet, Funktion
August 2013
HI-3593
3.3V ARINC 429 Dual Receiver,
Single Transmitter with SPI Interface
GENERAL DESCRIPTION
PIN CONFIGURATIONS (Top View)
The HI-3593 from Holt Integrated Circuits is a CMOS
integrated circuit for interfacing a Serial Peripheral
Interface (SPI) enabled microcontroller to the ARINC 429
serial bus. The device provides two receivers, each with
user-programmable label recognition for any combination
of 256 possible labels, 32 x 32 Receive FIFO, 3 priority-
label quick-access double-buffered registers and analog
line receiver. The independent transmitter has a 32 x 32
Transmit FIFO and built-in line driver. The line driver
operates from a single 3.3V supply and includes on-chip
DC/DC converter to generate the bipolar ARINC 429
differential voltage levels needed to directly drive the
ARINC 429 bus. The status of the transmit and receive
FIFOs and priority-label buffers can be monitored using
the programmable external interrupt pins, or by polling the
HI-3593 Status Registers. Other features include a
programmable option of data or parity in the 32nd bit, and
the ability to switch the bit-signifiance of ARINC 429 labels.
Pins are available with different input resistance and
output resistance values which provides flexibility when
using external lightning protection circuitry.
The Serial Peripheral Interface minimizes the number of
host interface signals resulting in a small footprint device
that can be interfaced to a wide range of industry-standard
microcontrollers supporting SPI. Alternatively, the SPI
signals may be controlled using just four general purpose
I/O port pins from a microcontroller or custom FPGA. The
SPI and all control signals are CMOS and TTL compatible
and support 3.3V operation.
The HI-3593 applies the ARINC 429 protocol to the
receivers and transmitter. ARINC 429 databus timing
comes from a 1 MHz clock input, or an internal counter can
derive it from higher clock frequencies having certain fixed
values, possibly the external host processor clock.
FEATURES
· ARINC 429 specification compliant
· Single 3.3V power supply
· On-chip analog line driver and receiver connect
directly to ARINC 429 bus
· Programmable label recognition for 256 labels
· 32 x 32 Receive FIFOs and Priority-Label buffers
· Independent data rates for Transmit and Receive
· 10MHz, four-wire Serial Peripheral Interface (SPI)
· Industrial & extended temperature ranges
-1
RIN1A-40 - 2
RIN1A - 3
RIN1B - 4
RIN1B-40 - 5
RIN2A-40 - 6
RIN2A - 7
RIN2B - 8
RIN2B-40 - 9
MR - 10
ACLK - 11
HI-3593PCI
HI-3593PCT
HI-3593PCM
33 - AMPA
32 - TXAOUT
31 - AMPB
30 - TXBOUT
29 -
28 - TFULL
27 - TEMPTY
26 - R1FLAG
25 - R1INT
24 - R2FLAG
23 - R2INT
44 - Pin Plastic 7mm x 7mm
Chip-Scale Package (QFN)
-1
RIN1A-40 - 2
RIN1A - 3
RIN1B - 4
RIN1B-40 - 5
RIN2A-40 - 6
RIN2A - 7
RIN2B - 8
RIN2B-40 - 9
MR - 10
ACLK - 11
HI-3593PQI
HI-3593PQT
HI-3593PQM
33 - AMPA
32 - TXAOUT
31 - AMPB
30 - TXBOUT
29 -
28 - TFULL
27 - TEMPTY
26 - R1FLAG
25 - R1INT
24 - R2FLAG
23 - R2INT
44 - Pin Plastic Quad Flat Pack (PQFP)
(DS3593 Rev. B)
HOLT INTEGRATED CIRCUITS
www.holtic.com
08/13






HI-3593 Datasheet, Funktion
HI-3593
RECEIVE STATUS REGISTER
(Receiver 1 Read, SPI Op-code 0x90)
(Receiver 2 Read, SPI Op-code 0xB0)
00
76543210
MSB
LSB
Bit Name
7X
6X
5 PL3
4 PL2
3 PL1
2 FFFULL
1 FFHALF
0 FFEMPTY
R/W Default Description
R 0 Not used. Always reads “0”
R 0 Not used. Always reads “0”
R 0 This bit is set when a message is received by Priority Label filter #3
R 0 This bit is set when a message is received by Priority Label filter #2
R 0 This bit is set when a message is received by Priority Label filter #1
R 0 This bit is set when the Receive FIFO contains 32 ARINC 429 messages
R 0 This bit is set when the Receive FIFO contains at least 16 ARINC 429 messages
R 1 This bit is set when the Receive FIFO is empty
TRANSMIT STATUS REGISTER
(Read, SPI Op-code 0x80)
00000
76543210
MSB
LSB
Bit Name
7X
6X
5X
4X
3X
2 TFFULL
1 TFHALF
0 TFEMPTY
R/W Default Description
R 0 Not used. Always reads “0”
R 0 Not used. Always reads “0”
R 0 Not used. Always reads “0”
R 0 Not used. Always reads “0”
R 0 Not used. Always reads “0”
R 0 This bit is set when the Transmit FIFO contains 32 ARINC 429 messages
R 0 This bit is set when the Transmit FIFO contains at least 16 ARINC 429 messages
R 1 This bit is set when the Transmit FIFO is empty
ACLK DIVISION REGISTER
(Write, SPI Op-code 0x38)
(Read, SPI Op-code 0xD4)
000
0
76543210
MSB
LSB
Bit Name
7X
6X
5X
4 - 1 DIV[3:0]
0X
R/W Default Description
R/W 0 Not used.
R/W 0 Not used.
R/W 0 Not used.
R/W 0 The value programmed in DIV[3:0] sets the ACLK division ratio (see table 2)
R/W 0 Not used.
HOLT INTEGRATED CIRCUITS
6

6 Page









HI-3593 pdf, datenblatt
HI-3593
FUNCTIONAL DESCRIPTION (cont.)
TRANSMITTER
SELF TEST
FIFO OPERATION
Figure 4 shows a block diagram of the HI-3593 transmitter. The
Transmit FIFO is loaded with ARINC 429 words awaiting
transmission. SPI op-code 0x0C writes each ARINC 429 word into
the FIFO, at the next available FIFO location. If Transmit Status
Register bit TFEMPTY equals “1” (FIFO empty), then up to 32 words
(32 bits each) may be loaded. If Transmit Status Register bit
TFEMPTY equals “0” then only the available positions may be
loaded. If all 32 positions are full, Transmit Status Register bit
TFFULL is asserted. Further attempts to load the Transmit FIFO are
ignored until at least one ARINC 429 word is transmitted.
The Transmit FIFO half-full flag (Transmit Status Register bit
TFHALF) equals “0” when the Transmit FIFO contains less than 16
words. When TFHALF equals “0”, the system microprocessor can
safely initiate a 16-word ARINC 429 write sequence.
If Transmit Control Register bit SELFTEST is equal ”1”, the
transmitter serial output data is internally looped-back into the
receiver 1. The data will appear inverted (compliment) on receiver 2.
Data passes unmodified from transmitter to receiver 1. Setting
Transmit Control register bit SELFTEST to ”1” forces TXAOUT and
TXBOUT to the Null state to prevent self-test data from appearing on
the ARINC 429 bus.
SYSTEM OPERATION
The receivers are independent of the transmitter. Therefore,
control of data exchanges is strictly at the option of the user. The
only restrictions are:
1. The received data will be overwritten if the Receive FIFO is
full and at least one location is not retrieved before the next
complete ARINC 429 word is received.
In normal operation (Transmit Control Register bit TPARITY = ”1”),
the 32nd bit transmitted is an odd parity bit. If Transmit Control
Register bit PARITY equals “0”, all 32 bits loaded into the Transmit
FIFO are treated as data and are transmitted.
The Transmit and Receive FIFOs may be cleared using Software
Reset (SPI op-code 0x44). The Transmit FIFO should be cleared
after a self-test before starting normal operation to avoid inadvertent
transmission of test data.
DATA TRANSMISSION
If Transmit Control Register bit TMODE equals “1”, ARINC 429 data
is transmitted immediately following the CS rising edge of the SPI
instruction that loaded data into the Transmit FIFO. Writing Transmit
Control Register bit TMODE to “0” allows the software to control
transmission timing; each time an SPI op-code 0x40 is executed, all
loaded Transmit FIFO words are transmitted. If new words are
loaded into the Transmit FIFO before transmission stops, the new
words will also be output. Once the Transmit FIFO is empty and
transmission of the last word is complete, the FIFO can be loaded
with new data which is held until the next SPI 0x40 instruction is
executed. Once transmission is enabled, the FIFO positions are
incremented with the top register loading into the data transmission
shift register. Within 2.5 data clocks the first data bit appears at
TXAOUT and TXBOUT. The 31 or 32 bits in the data transmission
shift register are presented sequentially to the outputs in the ARINC
429 format with the following timing:
2. The Transmit FIFO can store 32 words maximum and
ignores attempts to load additional data when full.
DC/DC CONVERTER
The HI-3593 requires only a single +3.3V power supply. An
integrated inverting / non-inverting voltage doubler generates the
rail voltages (+/- 6.6V) which then power the line driver to produce
the required +/- 5V ARINC 429 signal levels.
The internal dual-polarity charge pump requires four external
capacitors, two for each polarity generated by the doubler. Pins
CP+ and CP- connect the external “fly” capacitor, CFLY, to the
positive portion of the doubler, resulting in twice VDD at the V+
pin. An output “hold” capacitor, COUT, is placed between V+ and
GND. COUT should be ten times the size of CFLY. The inverting
negative portion of the converter works in a similar fashion, with
CFLY and COUT placed between CN+ / CN- and V- / GND
respectively (see block diagram page 2). Note that low ESR
capacitors rated for at least 10V should be used.
Recommended Values:
V+ / GND = 47µF
V- / GND = 47µF
CP+ / CP- = 0.47µF
CN+ / CN- = 2.2µF
ARINC DATA BIT TIME
DATA BIT TIME
NULL BIT TIME
WORD GAP TIME
HIGH SPEED
10 Clocks
5 Clocks
5 Clocks
40 Clocks
LOW SPEED
80 Clocks
40 Clocks
40 Clocks
320 Clocks
A word counter detects when all loaded positions have been
transmitted and sets the Transmit Status Register TFEMPTY bit
high.
TRANSMITTER PARITY
The parity generator counts the Ones in the 31-bit word. The 32nd
bit transmitted will make parity odd. Setting Transmit Control
Register bit TPARITY to “0” bypasses the parity generator, and
allows 32 bits of data to be transmitted.
LINE DRIVER OPERATION
The line driver in the HI-3593 directly drives the ARINC 429 bus.
The two ARINC 429 outputs (TXAOUT and TXBOUT) provide a
differential voltage to produce a +10V One, a -10V Zero, and a 0 Volt
Null. Transmit Control Register bit RATE controls both the
transmitter data rate and the slope of the differential output signal.
No additional hardware is required to control the slope.
Writing Transmit Control Register bit RATE to “0” causes a 100
Kbit/s data rate and a slope of 1.5 µs on the ARINC 429 outputs.
Setting RATE to “1” causes a 12.5 Kbit/s data rate and a slope of
10µs. Slope rate is set by an on-chip resistor and capacitor and
tested to be within ARINC 429 specification requirements.
HOLT INTEGRATED CIRCUITS
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