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HI-3597 Schematic ( PDF Datasheet ) - HOLTIC

Teilenummer HI-3597
Beschreibung Octal ARINC 429 Receivers
Hersteller HOLTIC
Logo HOLTIC Logo 




Gesamt 18 Seiten
HI-3597 Datasheet, Funktion
January, 2012
HI-3596, HI-3597, HI-3598, HI-3599
Octal ARINC 429 Receivers
with Label Recognition and SPI Interface
GENERAL DESCRIPTION
The HI-359x family from Holt Integrated Circuits are sili-
con gate CMOS ICs for interfacing up to eight ARINC
429 receive buses to a high-speed Serial Peripheral
Interface (SPI) enabled microcontroller. Each receiver
has user-programmable label recognition for up to 16
labels, a four-word data buffer (FIFO), and an on-chip
analog line receiver. Receive FIFO status can be moni-
tored using the programmable external interrupt pins,
or by polling the status register. Other features include
the ability to switch the bit-signifiance of the ARINC 429
label and to recognize the 32nd received ARINC bit as
either data or a parity flag. Some versions provide a digi-
tal transmit channel which can be utilized with an exter-
nal line driver such as HI-8570 to relay information from
multiple sources, for example sensors, to a single col-
lection point such as a flight computer and can also be
configured as a loopback test register for each receive
channel. Versions are also available with different input
resistance values to provide flexibility when using exter-
nal lightning protection circuitry. The SPI and all control
signals are CMOS and TTL compatible and support
3.3V or 5V operation.
32nd bit can be data or parity
Low Power
Industrial & extended temperature ranges
PIN CONFIGURATION (TOP VIEW)
ACLK - 1
SC__K - 2
CS - 3
SI - 4
SO - 5
MR - 6
TX1 - 7
TX0 - 8
RIN1A - 9
RIN1A-40 - 10
RIN1B-40 - 11
RIN1B - 12
- 13
HI-3598PQI
&
HI-3598PQT
39 - RIN8A
38 - RIN7B
37 - RIN7B-40
36 - RIN7A-40
35 - RIN7A
34 - RIN6B
33 - RIN6B-40
32 - RIN6A-40
31 - RIN6A
30 - RIN5B
29 - RIN5B-40
28 - RIN5A-40
27 - RIN5A
The HI-3596 and HI-3598 are full featured parts. The
HI-3597 and HI-3599 give the user the option of utilizing
a smaller 24-pin SOIC package with very little trade off in
features. In this case, a global interrupt flag is provided
instead of individual external FIFO interrupt pins. The
HI-3597 is identical to the HI-3599 except that it offers
the digital transmit feature and seven receive channels.
HI-3598 Full function, full pin-out version
52 - Pin Plastic Quad Flat Pack (PQFP)
FEATURES
ARINC 429 compliant
Up to 8 independent receive channels
Digital transmit channel (except HI-3599)
3.3V or 5.0V logic supply operation
On-chip analog line receivers connect directly to
ARINC 429 bus
Programmable label recognition for 16 labels per
channel
Independent data rate selection for each receiver
Four-wire SPI interface
Label bit-order control
ACLK - 1
SCK - 2
CS - 3
SI - 4
SO - 5
TX1 - 6
TX0 - 7
RIN2A - 8
RIN2B - 9
RIN3A - 10
RIN3B - 11
GND - 12
HI-3597
PSI
&
HI-3597
PST
24 - VDD
23 - FLAG
22 - RIN8B
21 - RIN8A
20 - RIN7B
19 - RIN7A
18 - RIN6B
17 - RIN6A
16 - RIN5B
15 - RIN5A
14 - RIN4B
13 - RIN4A
HI-3597 minimum footprint, reduced pin-out version
24 - Pin Plastic Small Outline package (SOIC)
(See page 13 for additional package pin configurations)
DS3598 Rev. C
HOLT INTEGRATED CIRCUITS
www.holtic.com
1
01/12






HI-3597 Datasheet, Funktion
HI-3596, HI-3597, HI-3598, HI-3599
ARINC 429 Data Format
Control Register bit CR9 controls how individual bits in
the received ARINC word are mapped to the HI-359x
SPI data word during data read operations. Table 5
describes this mapping.
Table 5.  SPI / ARINC bit-mapping
SPI / ARINC bit-mapping
SPI Order 1 2 - 22 23 24 25 26 27 28 29 30 31 32
ARINC bit 32 31 - 11 10 9 1 2 3 4 5 6 7 8
CR9 = 0
Data
ARINC bit 32 31 - 11 10 9 8 7 6 5 4 3 2 1
CR9 = 1
Data
RINA-40
RINA
RINB
RINB-40
VDD
GND
VDD
GND
DIFFERENTIAL
AMPLIFIERS
COMPARATORS
ONE
NULL
ZERO
Figure 3.  ARINC Receiver Input
The HI-359x family guarantees recognition of these lev-
els with a common mode Voltage with respect to GND
less than ±30V for the worst case condition (3.15V sup-
ply and 13V signal level).
The tolerances in the design guarantee detection of
the above levels, so the actual acceptance ranges are
slightly larger. If the ARINC signal is out of the actual
acceptance ranges, including the nulls, the chip rejects
the data.
ARINC 429 Receiver
ARINC Bus Interface
Figure 3 shows the input circuit for each on-chip ARINC
429 line receiver. The ARINC 429 specification requires
detection levels summarized in Table 6.
Receiver Logic Operation
Figure 4 is a block diagram showing the logic for each
receiver.
Bit Timing
The ARINC 429 specification defines timing tolerances
for received data according to Table 7.
Table 7.  ARINC 429 Receiver Timing Tolerances
Table 6.  ARINC 429 Detection Levels
STATE
ONE
NULL
ZERO
DIFFERENTIAL VOLTAGE
+6.5 Volts to +13 Volts
+2.5 Volts to -2.5 Volts
-6.5 Volts to -13 Volts
Bit Rate
Pulse Rise Time
Pulse Fall Time
Pulse Width
HIGH SPEED
100Kbps ± 1%
1.5 ± 0.5μs
1.5 ± 0.5μs
5μs ± 5%
LOW SPEED
12K - 14.5Kbps
10 ± 5μs
10 ± 5μs
34.5 to 41.7μs
HOLT INTEGRATED CIRCUITS
6

6 Page









HI-3597 pdf, datenblatt
HI-3596, HI-3597, HI-3598, HI-3599
Parameters
Output Current
(All outputs and Bi-
directional pins)
Output Capacitance
OPERATING VOLTAGE RANGE
OPERATING SUPPLY CURRENT
Symbol Test Conditions
Output Sink
Output Source
IOH
IOL
VOUT = 0.4V
VOUT = VDD -0.4V
CO
Limits
Min Typ Max
1.6 -
-
- - -1.0
Unit
mA
mA
- 15 - pF
VDD 3.15 - 5.25 V
IDD - 2.5 7.0 mA
Table 12.  AC electrical characteristics
VDD = 3.3V or 5.0V, GND = 0V, TA = Operating Temperature Range and fclk=1MHz ±0.1% with 60/40 duty cycle
Parameters
Symbol
SPI INTERFACE TIMING
SCK clock Period
CS active after last SCK rising edge
CS setup time to first SCK rising edge
CS hold time after last SCK falling edge
CS inactive between SPI instructions
SPI SI Data set-up time to SCK rising edge
SPI SI Data hold time after SCK rising edge
SCK rise time
SCK fall time
SCK high time
SCK low time
SO valid after SCK falling edge
SO high-impedance after SCK falling edge
RECEIVER TIMING
Delay - Last bit of received ARINC word to FLAG (Full or Empty) - Hi Speed
Delay - Last bit of received ARINC word to FLAG (Full or Empty) - Lo Speed
Received data available to SPI interface. FLAG to CS active
SPI receiver read
tCYC
tCHH
tCES
tCEH
tCPH
tDS
tDH
tSCKR
tSCKF
tSCKH
tSCKL
tDV
tCHZ
tRFLG
tRFLG
tRXR
tSPIF
Limits
Min Typ Max
130 -
25 -
10 -
10 -
30 -
10 -
30 -
--
--
45 -
25 -
--
--
-
-
-
-
-
-
-
10
10
-
-
65
65
- - 16
- - 126
0- -
- - 85
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
μs
ns
ns
HOLT INTEGRATED CIRCUITS
12

12 Page





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