PDF HI-3596 Data sheet ( Hoja de datos )

Número de pieza	HI-3596
Descripción	Octal ARINC 429 Receivers
Fabricantes	HOLTIC
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No Preview Available ! January, 2012 HI-3596, HI-3597, HI-3598, HI-3599 Octal ARINC 429 Receivers with Label Recognition and SPI Interface GENERAL DESCRIPTION The HI-359x family from Holt Integrated Circuits are sili- con gate CMOS ICs for interfacing up to eight ARINC 429 receive buses to a high-speed Serial Peripheral Interface (SPI) enabled microcontroller. Each receiver has user-programmable label recognition for up to 16 labels, a four-word data buffer (FIFO), and an on-chip analog line receiver. Receive FIFO status can be moni- tored using the programmable external interrupt pins, or by polling the status register. Other features include the ability to switch the bit-signifiance of the ARINC 429 label and to recognize the 32nd received ARINC bit as either data or a parity flag. Some versions provide a digi- tal transmit channel which can be utilized with an exter- nal line driver such as HI-8570 to relay information from multiple sources, for example sensors, to a single col- lection point such as a flight computer and can also be configured as a loopback test register for each receive channel. Versions are also available with different input resistance values to provide flexibility when using exter- nal lightning protection circuitry. The SPI and all control signals are CMOS and TTL compatible and support 3.3V or 5V operation. • 32nd bit can be data or parity • Low Power • Industrial & extended temperature ranges PIN CONFIGURATION (TOP VIEW) ACLK - 1 SC__K - 2 CS - 3 SI - 4 SO - 5 MR - 6 TX1 - 7 TX0 - 8 RIN1A - 9 RIN1A-40 - 10 RIN1B-40 - 11 RIN1B - 12 - 13 HI-3598PQI & HI-3598PQT 39 - RIN8A 38 - RIN7B 37 - RIN7B-40 36 - RIN7A-40 35 - RIN7A 34 - RIN6B 33 - RIN6B-40 32 - RIN6A-40 31 - RIN6A 30 - RIN5B 29 - RIN5B-40 28 - RIN5A-40 27 - RIN5A The HI-3596 and HI-3598 are full featured parts. The HI-3597 and HI-3599 give the user the option of utilizing a smaller 24-pin SOIC package with very little trade off in features. In this case, a global interrupt flag is provided instead of individual external FIFO interrupt pins. The HI-3597 is identical to the HI-3599 except that it offers the digital transmit feature and seven receive channels. HI-3598 Full function, full pin-out version 52 - Pin Plastic Quad Flat Pack (PQFP) FEATURES • ARINC 429 compliant • Up to 8 independent receive channels • Digital transmit channel (except HI-3599) • 3.3V or 5.0V logic supply operation • On-chip analog line receivers connect directly to ARINC 429 bus • Programmable label recognition for 16 labels per channel • Independent data rate selection for each receiver • Four-wire SPI interface • Label bit-order control ACLK - 1 SCK - 2 CS - 3 SI - 4 SO - 5 TX1 - 6 TX0 - 7 RIN2A - 8 RIN2B - 9 RIN3A - 10 RIN3B - 11 GND - 12 HI-3597 PSI & HI-3597 PST 24 - VDD 23 - FLAG 22 - RIN8B 21 - RIN8A 20 - RIN7B 19 - RIN7A 18 - RIN6B 17 - RIN6A 16 - RIN5B 15 - RIN5A 14 - RIN4B 13 - RIN4A HI-3597 minimum footprint, reduced pin-out version 24 - Pin Plastic Small Outline package (SOIC) (See page 13 for additional package pin configurations) DS3598 Rev. C HOLT INTEGRATED CIRCUITS www.holtic.com 1 01/12 1 page HI-3596, HI-3597, HI-3598, HI-3599 FUNCTIONAL DESCRIPTION Control Word Register Each HI-359x receive channel is assigned a 16-bit Control Register which configures that receiver. Con- trol Register bits CR15 - CR0 are loaded from a 16-bit data value appended to SPI instruction n4 hex, where “n” is the channel number 1-8 hex. Writing to the Con- trol Register also clears the data FIFO for that channel. The Control Register contents may be read using SPI instruction n5 hex. Table 3 summarizes the Control Reg- ister bits functions. Table 3. Control Register Bits Functions CR Bit Function State Description CR0 (LSB) Receiver Data Rate Select 0 Data rate = ACLK/10 (ARINC 429 High-Speed) 1 Data rate = ACLK/80 (ARINC 429 Low-Speed) CR1 RFLAG Definition 0 FLAG goes high when receive FIFO is not empty (Contains at least one word) 1 FLAG goes high when receive FIFO is full CR2 Enable Label Recognition 0 Label recognition disabled 1 Label recognition enabled CR3 Reset Receiver 0 Normal Operation Reset this receiver (Clear receiver 1 logic and FIFO). The receive channel is disabled if CR3 is left high Receiver 0 Receiver parity check disabled CR4 Parity Check Enable 1 Receiver odd parity check enabled CR5 Self-Test (Loopback) CR6 Receiver Decoder CR7 - CR8 - CR9 CR10 to CR15 (MSB) ARINC Label Bit Order Not Used 0 Receiver’s inputs are connected to the Transmit Register serial data output. 1 Normal operation 0 Receiver Decoder Disabled 1 ARINC bits 10 and 9 must match CR7 and CR8 - If receiver decoder is enabled, the ARINC bit 10 must match this bit - If receiver decoder is enabled, the ARINC bit 9 must match this bit 0 Label bit order reversed (See Table 5) 1 Label bit order same as received (See Table 5) X Control register read returns “0” for these bits Status Register The HI-359x devices have a single 16-bit Status Reg- ister which is read to determine status for the eight received data FIFOs. The Status Register is read using SPI instruction n6 hex. Table 4 summarizes the Status Register bits functions. Table 4. Status Register Bits Functions CR Bit Function State Description SR0 Receiver 1 (LSB) FIFO Empty Receiver 1 FIFO contains valid data. 0 Resets to Zero when all data has been read. FLAG pin reflects the state of this bit when CR1=”0” 1 Receiver 1 FIFO is empty SR1 Receiver 2 FIFO Empty SR2 to SR6 Receiver 3 to Receiver 7 FIFO Empty SR7 Receiver 8 FIFO Empty SR8 Receiver 1 FIFO Full SR9 Receiver 2 FIFO Full SR10 to SR14 Receiver 3 to Receiver 7 FIFO Full SR15 (MSB) Receiver 8 FIFO Full 0 Receiver 2 FIFO contains valid data. 1 Receiver 2 FIFO is empty :: :: :: :: 0 Receiver 8 FIFO contains valid data. 1 Receiver 8 FIFO is empty Receiver 1 FIFO not full. FLAG pin 0 reflects the state of this bit when CR1=”1” Receiver 1 FIFO full. To avoid data 1 loss, the FIFO must be read within one ARINC word period. 0 Receiver 2 FIFO not full. 1 Receiver 2 FIFO full. :: :: :: :: 0 Receiver 8 FIFO not full. 1 Receiver 8 FIFO full. HOLT INTEGRATED CIRCUITS 5 5 Page HI-3596, HI-3597, HI-3598, HI-3599 ABSOLUTE MAXIMUM RATINGS Supply Voltages VDD ...................................................... -0.3 to +7.0V Power dissipation at 25oC Plastic Quad Flat Pack .......................... 1.5 W, derate 10mW/oC Voltage at pins RIN1A, RIN1B, RIN2A, RIN2B ........... -29V to +29V DC Current Drain per pin ........................................................ ±10mA Voltage at any other pin ......................................... -0.3V to VDD+0.3V Storage Temperature Range ................................... -65oC to +150oC Solder temperature (Leads) ............................ 280oC for 10 seconds Operating Temperature Range (Industrial) ................ -40°C to +85°C (Package) .................................................... 220oC (Extended Temp) .............. -55oC to +125oC NOTE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS Table 11. DC Electrical Characteristics VDD = 3.3V or 5.0V, GND = 0V, TA = Operating Temperature Range (unless otherwise stated) Parameters Symbol Test Conditions Limits Unit Min Typ Max ARINC INPUTS - Pins RINA, RINB, RINA-40 (with external 40KΩ), RINB-40 (with external 40KΩ) Differential Input Voltage (RIN1A to RIN1B, RIN2A to RIN2B, etc.) Input Resistance Input Current Inpit Capacitance (Guaranteed but not tested) LOGIC INPUTS ONE ZERO NULL Differential To GND To VDD Input Sink Input Source Differential To GND To VDD VIH VIL VNUL RI RG RH IIH IIL CI CG CH Common mode voltages less than ±30V with respect to GND (RINA to RINB) 6.5 -13.0 -2.5 - - - - -450 - - - 10.0 -10.0 0 140 140 100 - - - - - 13.0 -6.5 2.5 - - - 200 - 20 20 20 V V V kΩ kΩ kΩ μA μA pF pF pF Input Voltage Input Current LOGIC OUTPUTS Input Voltage HI Input Voltage LO Input Sink Input Source Pull-down Current (MR, SI, SCK, ACLK pins) Pull-up Current (CS) VIH VIL IIH IIL IPD IPU 70% VDD - - V - - 30% VDD V - - 1.5 μA -1.5 - - μA 250 - 600 μA -600 - -250 μA Output Voltage Logic “1” Output Voltage Logic “0” Output Voltage VOH VOL IOH = -100μA IOL = 1.0mA 90% VDD - - V - - 10% VDD V HOLT INTEGRATED CIRCUITS 11 11 Page

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