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8T39S06A Schematic ( PDF Datasheet ) - IDT

Teilenummer 8T39S06A
Beschreibung Crystal or Differential to Differential Clock Fanout Buffer
Hersteller IDT
Logo IDT Logo 




Gesamt 30 Seiten
8T39S06A Datasheet, Funktion
Crystal or Differential to
Differential Clock Fanout Buffer
8T39S06A
Datasheet
General Description
The 8T39S06A is a high-performance clock fanout buffer. The input
clock can be selected from two differential inputs or one crystal input.
The internal oscillator circuit is automatically disabled if the crystal
input is not selected. The crystal pin can be driven by a single-ended
clock.The selected signal is distributed to six differential outputs
which can be configured as LVPECL, LVDS or HCSL outputs. In
addition, an LVCMOS output is provided. All outputs can be disabled
into an high-impedance state. The device is designed for a signal
fanout of high-frequency, low phase-noise clock and data signal. The
outputs are at a defined level when inputs are open or tied to ground.
It is designed to operate from a 3.3V or 2.5V core power supply, and
either a 3.3V or 2.5V output operating supply.
Features
Two differential reference clock input pairs
Differential input pairs can accept the following input
levels: LVPECL, LVDS, HCSL, HSTL and Single-ended
Crystal Oscillator Interface
Crystal input frequency range: 10MHz to 40MHz
Maximum Output Frequency
LVPECL - 2GHz
LVDS - 2GHz
HCSL - 250MHz
LVCMOS - 250MHz
Two banks, each has three differential output pairs that can be
configured as LVPECL or LVDS or HCSL
One single-ended reference output with synchronous enable to
avoid clock glitch
Output skew: 80ps (maximum)
(Bank A and Bank B at the same output level)
Part-to-part skew: 200ps (typical)
Additive RMS phase jitter @ 156.25MHz, (12kHz - 20MHz):
34.7fs (typical), 3.3V/ 3.3V
Supply voltage modes:
VDD/VDDO
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
-40°C to 85°C ambient operating temperature
Lead-free (RoHS 6) packaging
©2016 Integrated Device Technology, Inc.
1
May 20, 2016






8T39S06A Datasheet, Funktion
8T39S06A Datasheet
Function Tables
Table 3: REF_SELx Function Table
Control Input
Selected Input Reference Clock
REF_SEL[1:0]
00 (default)
CLK0, nCLK0
01 CLK1, nCLK1
10 XTAL
11 XTAL
Table 4: OE_SE Function Table
OE_SE
REFOUT
0 (default)
High-Impedance
1 Enabled
NOTE: Synchronous output enable to avoid clock glitch.
Table 5: Input/Output Operation Table, OE_SE
Input Status
OE_SE
REF_SEL [1:0] CLKx and nCLKx
0 (default)
Don’t care
Don’t Care
1
10 or 11
Don’t Care
CLK0 and nCLK0 are both open circuit
CLK0 and nCLK0 are tied to ground
1 00 (default)
CLK0 is high, nCLK0 is low
CLK0 is low, nCLK0 is high
CLK1 and nCLK1 are both open circuit
CLK1 and nCLK1 are tied to ground
1 01
CLK1 is high, nCLK1 is low
CLK1 is low, nCLK1 is high
Output State
REFOUT
High-Impedance
Fanout Crystal Oscillator
Logic Low
Logic Low
Logic High
Logic Low
Logic Low
Logic Low
Logic High
Logic Low
©2016 Integrated Device Technology, Inc.
6
May 20, 2016

6 Page









8T39S06A pdf, datenblatt
8T39S06A Datasheet
Table 16: LVPECL DC Characteristics, VDDOA = VDDOB = 2.5V±5%, GND = 0V,
TA = -40°C to 85°C1
Symbol Parameter
Test Conditions
Minimum
VOH Output High Voltage2
VOL Output Low Voltage2
VDDOX – 1.4
VDDOX – 2.0
VSWING
Peak-to-Peak Output
Voltage Swing
0.4
Typical
NOTE 1.VDDOX denotes VDDOA and VDDOB.
NOTE 2.Outputs terminated with 50to VDDOX – 2V.
Table 17: LVDS DC Characteristics, VDDOA = VDDOB = 3.3V±5%, GND = 0V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
VOD
VOD
VOS
VOS
Differential Output Voltage
VOD Magnitude Change
Offset Voltage
VOS Magnitude Change
247
1.025
50
50
Maximum
VDDOX – 0.8
VDDOX – 1.6
1.0
Units
V
V
V
Maximum
454
1.375
Units
mV
mV
V
mV
Table 18: LVDS DC Characteristics, VDDOA = VDDOB = 2.5V±5%, GND = 0V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
VOD
VOD
VOS
VOS
Differential Output Voltage
VOD Magnitude Change
Offset Voltage
VOS Magnitude Change
247
1.025
50
50
Maximum
454
1.375
Units
mV
mV
V
mV
Table 19: Crystal Characteristics
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Capacitive Loading (CL)
Test Conditions
Minimum
10
Typical
Fundamental
12
Maximum
40
50
7
18
Units
MHz
pF
pF
©2016 Integrated Device Technology, Inc.
12
May 20, 2016

12 Page





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